Browsing by Author "Liu, Jun-Cheng"

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Characteristics of atomic-layer-deposited Al(2)O(3) high-k dielectric films grown on Ge substrates
(2008)
Cheng, Chao-Ching
;
Chien, Chao-Hsin
;
Luo, Guang-Li
;
Liu, Jun-Cheng
;
Kei, Chi-Chung
This paper describes the structural and electrical properties of Al(2)O(3) thin films grown through atomic layer deposition onto Ge substrates over a wide deposition temperature range (50-300 degrees C). From grazing-incidence X-ray reflectivity and X-ray photoelectron spectroscopy, we found that increasing the deposition temperature improved the Al(2)O(3) film density and its dielectric stoichiometry; nevertheless, dielectric intermixing between main Al(2)O(3) and interfacial GeO(2) appeared at temperatures above 200 degrees C, along with degradation of the GeO(2)/Ge interface. Accordingly, a relatively large gate leakage current (J(g)) and a high density of interfacial states D(it) (> 10(13) cm(-2) eV(-1)) were observed as a result of deterioration of the entire Al(2)O(3)/Ge structure at higher deposition temperatures. In addition, although subsequent high-temperature processing at 600 degrees C in a N(2) ambient could relieve the oxygen-excessive behavior further, i.e., to provide a more stoichiometric film, the accompanying GeO(x) volatilization close to the dielectric interface caused greater damage to the electrical performance. Only forming gas annealing (H(2)/N(2), 1:10) at low temperature (300 degrees C) improved the capacitance-voltage characteristics of the Pt/Al(2)O(3)/Ge structure, in terms of providing a lower value of D(it) (ca. 6 x 10(11) cm(-2) eV(-1)), a lower value of J(g), and a reduced hysteresis width.
Effects of Minority-Carrier Response Behavior on Ge MOS Capacitor Characteristics: Experimental Measurements and Theoretical Simulations
(2009-05-01)
Cheng, Chao-Ching
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Chien, Chao-Hsin
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Luo, Guang-Li
;
Ling, Yu-Ting
;
Chang, Ruey-Dar
In this paper, we present MEDICI simulations of the admittance-voltage properties of Ge and Si MOS devices, including analyses of substrate conductance Grub and high-low transition frequency f(tran), to explore the differences in the minority-carrier response. The Arrhenius-dependent G(sub) characteristics revealed that a larger energy loss-by at least four orders of magnitude-occurs in Ge than in Si, reflecting the fast minority-carrier response rate, i.e., a higher value of f(tran). We confirmed that the higher intrinsic carrier concentration in Ge, through the generation/recombination of midgap trap levels as well as the diffusion mechanism, resulted in the onset of low-frequency C-V curves in the kilohertz regime, accompanying the gate-independent inversion conductance. The experimental data obtained from Al(2)O(3)/Ge MOS capacitors were consistent with the values of G(sub) and f(tran) obtained from MEDICI predictions and theoretical calculations. In addition, upon increasing the inversion biases, we observed shifts in the G(sub/)f conductance peaks to low frequencies that mainly arose from the transition of minority carriers with bulk traps in the depletion layer. Meanwhile, we estimated that the bulky defects of ca. (2-4) x 10(15) cm(-3) exist in present-day low-doped Ge wafers.
Five-element circuit model using linear-regression method to correct the admittance measurement of metal-oxide-semiconductor capacitor
(2009-01-01)
Cheng, Chao-Ching
;
Chien, Chao-Hsin
;
Luo, Guang-Li
;
Liu, Jun-Cheng
;
Chen, Yi-Cheng
The authors present a linear-regression method based on a five-element circuit model to correct measured capacitance-voltage and conductance-voltage curves. This model explains the effects of series resistance and parasitic capacitance/inductance on the frequency dispersion of measured capacitance and the magnification of measured conductance. These extracted parasitic components show significant dependencies on the geometry of capacitor structure, thereby causing different frequency-dependent capacitance characteristics in measurements. (C) 2009 American Vacuum Society. [DOI: 10.1116/1.3058724]
Junction and Device Characteristics of Gate-Last Ge p- and n-MOSFETs With ALD-Al(2)O(3) Gate Dielectric
(2009-08-01)
Cheng, Chao-Ching
;
Chien, Chao-Hsin
;
Luo, Guang-Li
;
Lin, Ching-Lun
;
Chen, Hung-Sen
In this paper, we investigated the characteristics of Ge junction diodes and gate-last p- and n-metal-oxide-semiconductor field-effect transistors with the atomic-layer-deposited-Al(2)O(3) gate dielectrics. The magnitudes of the rectifying ratios for the Ge p(+)-n and n(+)-p junctions exceeded three and four orders of magnitude (in the voltage range of +/-1 V), respectively, with accompanying reverse leakages of ca. 10(-2) and 10(-4) A . cm(-2), respectively. The site of the primary leakage path, at either the surface periphery or junction area, was determined by the following conditions: 1) the thermal budget during dopant activation, and 2) whether forming gas annealing (FGA) was employed or not. In addition, performing FGA at 300 degrees C boosted the device on-current, decreased the Al(2)O(3)/Ge interface states to 8 x 10(11) cm(-2) . eV(-1), and improved the reliability of bias temperature instability. The peak mobility and on/off ratio reached as high as 225 cm(2) . V(-1) . s(-1) and > 10(3), respectively, for the p-FET (W/L = 100 mu m/4 mu m), while these values were less than 100 cm(2) . V(-1) . s(-1) and ca. 10(3), respectively, for the n-FET (W/L = 100 mu m/9 mu m). The relatively inferior n-FET performance resulted from the larger source/drain contact resistance, higher surface states scattering, and lower substrate-doping concentration.
Junction and Device Characteristics of Gate-Last Ge p- and n-MOSFETs With ALD-Al2O3 Gate Dielectric
(2009-08-01)
Cheng, Chao-Ching
;
Chien, Chao-Hsin
;
Luo, Guang-Li
;
Lin, Ching-Lun
;
Chen, Hung-Sen
In this paper, we investigated the characteristics of Ge junction diodes and gate-last p- and n-metal-oxide-semiconductor field-effect transistors with the atomic-layer-deposited-Al2O3 gate dielectrics. The magnitudes of the rectifying ratios for the Ge p(+)-n and n(+)-p junctions exceeded three and four orders of magnitude (in the voltage range of +/-1 V), respectively, with accompanying reverse leakages of ca. 10(-2) and 10(-4) A . cm(-2), respectively. The site of the primary leakage path, at either the surface periphery or junction area, was determined by the following conditions: 1) the thermal budget during dopant activation, and 2) whether forming gas annealing (FGA) was employed or not. In addition, performing FGA at 300 degrees C boosted the device on-current, decreased the Al2O3/Ge interface states to 8 x 10(11) cm(-2) . eV(-1), and improved the reliability of bias temperature instability. The peak mobility and on/off ratio reached as high as 225 cm(2) . V-1 . s(-1) and > 10(3), respectively, for the p-FET (W/L = 100 mu m/4 mu m), while these values were less than 100 cm(2) . V-1 . s(-1) and ca. 10(3), respectively, for the n-FET (W/L = 100 mu m/9 mu m). The relatively inferior n-FET performance resulted from the larger source/drain contact resistance, higher surface states scattering, and lower substrate-doping concentration.