Browsing by Author "Liu, Lenvis"

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Grain Boundary Trap-Induced Current Transient in a 3-D NAND Flash Cell String
(2019-04-01)
Lin, Wei-Liang
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Tsai, Wen-Jer
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Cheng, C. C.
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Ku, S. H.
;
Liu, Lenvis
Transient cell current caused by the trapping/detrapping of grain boundary traps in the polycrystalline silicon (poly-Si) channel of a 3-D NAND cell string is comprehensively studied in this paper. This transient has a time constant of 10 mu s or longer and is strongly dependent on the bias history. It is also affected by the trap distribution as revealed by TCAD simulations. Sensing offset between program verify and read results in "pseudo" charge loss/gain that reduces the sensing margin. The posttreatment of the poly-Si channel is suggested to mitigate this effect.
Hot-Carrier Injection-Induced Disturb and Improvement Methods in 3D NAND Flash Memory
(2019-01-01)
Lin, Wei-Liang
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Tsai, Wen-Jer
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Cheng, C. C.
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Lu, Chun-Chang
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Ku, S. H.
We investigate a hot-carrier injection- induced program disturb in a 3D NAND flash memory. As there exist specific coding patterns, a "down-coupling" region and a "pre-charge" regions are formed during program-verify and the following program phases, respectively, in the inhibit cell strings. A high heating field is built nearby the PGM wordline. Hot carriers may inject into the inhibit cells as Vpgm is applied. Soft ramp-down and pre-turn-on schemes are proposed to mitigate this disturb.
Investigation of charge loss in cycled NBit cells via field and temperature accelerations
(2006)
Tsai, W. J.
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Zous, N. K.
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Chen, H. Y.
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Liu, Lenvis
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Yeh, C. C.
In nitride storage flash memories, the high-V-T state retention loss induced by field and temperature acceleration is compared between single cells and products. Our result reveals that the charge loss path is the same no matter which accelerating methods is used. The traps created at the bottom oxide during P/E cycling provide such leak paths. In addition, the annealing of interface states would play a role in the V-T loss during high-temperature bake.
Poly-Silicon Trap Position and Pass Voltage Effects on RTN Amplitude in a Vertical NAND Flash Cell String
(2016-08)
Chou, Y. L.
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Wang, Tahui
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Lin, Mercator
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Chang, Y. W.
;
Liu, Lenvis
We investigate the dependence of random telegraph noise (RTN) on a poly-silicon trap position in a 3D vertical channel and charge-trapping NAND flash cell string. We characterize RTN in read current of each cell of a string at different read and pass voltages. RTN characteristics resulting from a trap in a read cell or in a pass cell are differentiated. A method to identify a poly-silicon trap position in a NAND string is proposed. We perform the 3D TCAD simulation to calculate channel electron density in a string. Measured RTN characteristics can be explained by current-path percolation and channel carrier screening effects. The distribution of RTN amplitudes in NAND strings is characterized.
Polycrystalline-Silicon Channel Trap Induced Transient Read Instability in a 3D NAND Flash Cell String
(2016-01-01)
Tsai, Wen-Jer
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Lin, W. L.
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Cheng, C. C.
;
Ku, S. H.
;
Chou, Y. L.
Vt instability caused by grain-boundary trap (GBT) in the poly-crystalline silicon (poly-Si) channel of a 3D NAND string are comprehensively studied. Experimental results reveal that trapping/detrapping of GBT would cause transient cell current with a time constant of lOus or longer, and this transient is strongly affected by the bias history. Sensing offset between program/erase verify (PV/EV) and read (RD) results in "pseudo" charge loss/gain that reduces the sensing margin. Modified EV, PV, or RD bias schemes are suggested to mitigate this effect.