Browsing by Author "Liu, P. W."

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A New and Simple Experimental Approach to Characterizing the Carrier Transport and Reliability of Strained CMOS Devices in the Quasi-Ballistic Regime
(2009)
Hsieh, E. R.
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Chung, Steve S.
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Liu, P. W.
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Chiang, W. T.
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Tsai, C. H.
A new yet simple approach, V(D,sat) method, without complicate temperature measurement setup, has been developed to investigate the carrier transport characteristics for MOSFET devices in the quasi-ballistic regime. It has shown quite good matches with that of Temperature Dependent Method (TDM) developed from the quantum theory [1]. For the first time, the carrier transport properties after HC stress were also examined based on the proposed method. Moreover, method has been applied to examine the carrier transport and reliabilities in advanced strain-CMOS devices. In terms of the device performance, the enhancement of the drain current is strongly related to the transport parameter, the injection velocity, V(inj) which serves as a good monitor for the strain design and current enhancement. While, considering the device reliability after the HC stress, ballistic efficiency, B(sat) is responsible for the I(D) degradation as a result of the increase in interface scatterings. Finally, a roadmap of the V(inj) from those reported results has been provided which serves as a good reference for designing high performance strain-based CMOS devices.
A New Observation of Strain-Induced Slow Traps in Advanced CMOS Technology with Process-Induced Strain Using Random Telegraph Noise Measurement
(2009)
Lin, M. H.
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Hsieh, E. R.
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Chung, Steve S.
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Tsai, C. H.
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Liu, P. W.
In this paper, the hot-carrier induced oxide trap and its correlation with enhanced degradation in strained CMOS devices have been reported for the first time. First, the I(D)-RTN (Drain Current Random Telegraph Noise) has been employed to study the HC stress induced slow oxide traps in strained nMOSFETs and pMOSFETs. Secondly, different behavior of the slow traps in nMOSFET and pMOSFET has been observed. Results show that the vertical compressive strain generates extra oxide defects and induces more scattering after the HC stress in CESL nMOSFET. This vertical strain in CESL, also contributes to a non-negligible amount of extra device degradation. While, SiGe S/D pMOSFET shows different behavior in that the compressive strain in this structure shows no impact on its reliability.
Design of High-Performance and Highly Reliable nMOSFETs with Embedded Si:C S/D Extension Stressor(Si:C S/D-E)
(2009)
Chung, Steve S.
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Hsieh, E. R.
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Liu, P. W.
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Chiang, W. T.
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Tsai, S. H.
A Novel strained nMOSFET with embedded Si:C in S/D extension stressor (Si:C S/D-E) was presented. Comparing to the bulk device, it revealed good drive current ION (+27%), high I(D.sat) current (+67%), enhanced channel mobility (+105%), at a lower effective substitutional carbon concentration (C%-1.1%), using the poly-gate 40nm-node Si:C/eSiGe S/D CMOS technology. Moreover. PBTI effect was first observed in this device as a result of Carbn impurity out-diffusion, which is of critically important for the design trade-off between performance and reliability.
More Strain and Less Stress- The Guideline for Developing High-End Strained CMOS Technologies with Acceptable Reliability
(2008)
Chung, Steve S.
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Hsieh, E. R.
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Huang, D. C.
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Lai, C. S.
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Tsai, C. H.
In this paper, the design guideline with emphasis on CMOS device reliability has been addressed. Advanced 65nm CMOS devices with various strain engineering were evaluated. For nMOSFETs, charge pumping (CP) measurement is efficient for their reliability characterizations. Although biaxial strained SiGe-channel device provides good driving current enhancement, it suffers from the Ge out-diffusion such that exhibits worse reliability. The SSOI device exhibits good hot-carrier immunity, but its interface quality needs special care during the process. In addition, SiC on S/D device is an alternative for high current enhancement, but its off-state junction leakage is serious. Then, CESL device becomes the most promising technology with high performance and the best reliability, especially with process simplicity. For pMOSFETs, both uniaxial and biaxial strained devices have been studied. For the first time, an accurate representation of interface trap (Nit) profiling, suitable for HC and NBTI analyses, has been developed by an improved DCIV method. The uniaxial-strained device shows much better reliability, in particular a special class of SiGe S/D device with EDB design seems to be promising. These results provide a valuable guideline for the aggressive design of strained CMOS technologies.
New Observation of an Abnormal Leakage Current in Advanced CMOS Devices with Short Channel Lengths Down to 50nm and Beyond
(2008)
Hsieh, E. R.
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Chung, Steve S.
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Lin, Y. H.
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Tsai, C. H.
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Liu, P. W.
In this work, for the first time, an abnormal leakage current has been observed in MOSFET with 50nm channel length and beyond. This effect shows that, in an ultra-short channel MOSFET, sub-threshold swing (SS) and I(off) are decreased for back-biased nMOSFET and pMOSFET. This effect is attributed to the BJT-induced current from the source to the drain. An experimental approach has been used to verify the existence of this BJT current component. As a consequence, this BIT current can be reduced with appropriate control of the S/D-to-substrate junction. As an application of the approach to advanced embedded-SiC MOSFET with various splits, it was found that a higher band-offset of S/D-to-substrate junction will give rise to a larger the BJT ballistic transport current. This provides us important information on reducing the leakage current for advanced CMOS with 50nm and beyond.
New observations on the uniaxial and biaxial strain-induced hot carrier and NBTI Reliabilities for 65nm node CMOS devices and beyond
(2006)
Chung, Steve S.
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Huang, D. C.
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Tsai, Y. J.
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Lai, C. S.
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Tsai, C. H.
In this paper, new observations on the uniaxial and biaxial strain-induced hot carrier reliability and/or NBTI in nMOSFET and pMOSFET respectively have been reported for the first time. Uniaxial and biaxial strained nMOSFET and pMOSFET have been extensively examined. Different mechanisms are responsible for different strains in nMOSFET and pMOSFET. For the nMOFETs, it was found that uniaxial strain device has comparable HC reliability with the control device, while biaxial SiGe-strained device exhibits a much worse reliability. This is related to a large impact ionization rate in a biaxial strain which leads to a much worse reliability. For the pMOSFETs, either uniaxial or biaxial strained device shows a comparable amount of HC degradation, while SiGe S/D strained structure might be better considering process complexity, performance, and reliability Although NBTI is still a great concern in SiGe S/D devices, embedded SiGe S/D technique can improve greatly the device NBTI reliability. These results provide a valuable guideline for the present 65nm and beyond CMOS device design with focus on the strain engineering.
Technology roadmaps on the ballistic transport in strain engineered nanoscale CMOS devices
(2007)
Chung, Steve S.
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Tsai, Y. J.
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Tsai, C. H.
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Liu, P. W.
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Lin, Y. H.
As device channel length continues to scale beyond 90nm, carrier transport in the ballistic regime becomes critically important. In this paper, the strain engineering and its correlation to the ION current enhancement of CMOS devices in the ballistic regime has been examined. It was characterized by two parameters, the ballistic transport efficiency and the injection velocity. Experimental verifications on very high mobility n- and p-MOSFET channel/substrate orientations with various strains have been made. For nMOSFETs, it shows that uniaxial tensile-stress using CESL is more efficient in current enhancement than the biaxial stress with bulk strained-SiGe technique. For the pMOSFETs, compressive stress using uniaxial or biaxial has been evaluated for various structures. It was found that both ballistic efficiency and the injection velocity can be enhanced in a specific pMOS structure with appropriate combination of CESL and biaxial strain. The technology roadmaps have then been established from advanced 65nm CMOS devices. These results provide a guideline for designing high performance strained technology for CMOS devices in the sub-100nm regime.
The channel backscattering characteristics of sub-100nm CMOS devices with different channel/substrate orientations
(2007)
Tsai, Y. J.
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Chung, Steve S.
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Liu, P. W.
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Tsai, C. H.
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Lin, Y. H.
The channel backscattering and injection velocity of carriers in advanced CMOS devices are the two key parameters for achieving high drain current enhancement. For the first time, an extensive study of these transport parameters for different substrate orientations has been evaluated for both nMOSFET and pMOSFET. By suitably choosing the substrate orientation, it may achieve a reduced backscattering and an increased injection velocity, which is preferable for designing high performance logic CMOS devices. Results show that, in pMOSFET, (110) substrate is preferred and current enhancement can be greatly enhanced in the < 112 > channel. In comparison, (110) substrate in nMOSFET has an adverse effect in reducing driving current as a result of poorer transport characteristics. Therefore, (100) substrate is expected for nMOSFET design. A guideline is then summarized for the optimum design of high performance CMOS devices.
The Understanding of Strain-Induced Device Degradation in Advanced MOSFETs with Process-Induced Strain Technology of 65nm Node and Beyond
(2010)
Lin, M. H.
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Hsieh, E. R.
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Chung, Steve S.
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Tsai, C. H.
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Liu, P. W.
In this paper, the origin of the strained-induced degradation in the MOSFETs with process-induced strain has been investigated by the ID-RTN ( Drain Current Random Telegraph Noise) technique. The process-induced strain on devices will make worse the device reliability, as reported in [1-2]. First, the ID-RTN has been employed to study the reliability of two different types of strain devices, i.e., the CESL strain and SiC S/D strain on nMOSFETs. Both CESL and SiC S/D nMOSFETs exhibit poorer reliability compared to bulk devices. However, their impacts to the much worse degradation are different. Results demonstrated that, for the strain in CESL device, it introduced extra mobility scattering in the vertical direction, while in SiC S/D device, the tensile strain along the channel causes an increase of trap generation via the horizontal field only. The CESL process introduces an additional compressive strain vertical to the channel such that it shows much worse reliability than the SiC S/D ones.