Browsing by Author "Liu, Rich"

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A 2-bit/cell, maskless, self-aligned resistance memory with high thermal stability
(2007)
He, ChiaHua
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Lee, Ming-Daou
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Pan, Chen-Ling
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Lai, Erb-Kun
;
Yao, Yeong-Der
We report the first demonstration of a multilevel cell (MLC) resistance device using a self-aligned WO, film prepared by plasma oxidation. The 2-bit/cell operation is achieved by applying a series of 1.5V programming pulses. The device shows high thermal stability and good data retention. The resistance change can be attributed to variable-range hopping and Ohmic transport mechanisms. This device has the potential for future low-voltage, 3-dimentioanl nonvolatile memory with multiple bits per layer. In addition, no additional mask is needed to form the self-aligned device.
A highly reliable self-aligned graded oxide WOx resistance memory: Conduction mechanisms and reliability
(2007-01-01)
Ho, ChiaHua
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Lai, E. K.
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Lee, M. D.
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Pan, C. L.
;
Yao, Y. D.
WOx formed by plasmas oxidation shows promising multibit/cell resistance memory characteristics [1]. The simple memory is completely self-aligned, requiring no additional masks and has a small 6F(2) cell size. In this work we introduce a graded oxide device that is highly reliable (250 degrees C baking for > 2,000 hrs). The conduction mechanism and factors affecting the memory reliability are examined extensively.
A study of gate-sensing and channel-sensing (GSCS) transient analysis method - Part II: Study of the intra-nitride behaviors and reliability of SONOS-type devices
(2008-08-01)
Du, Pei-Ying
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Lue, Hang-Ting
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Wang, Szu-Yu
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Huang, Tiao-Yuan
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Hsieh, Kuang-Yeu
For the first time, we can directly investigate the charge transport and intra-nitride behaviors of SONOS-type devices by exploiting the gate-sensing and channel-sensing (GSCS) method. Our results clearly indicate that for electron injection (+FN program), the electron centroid migrates from the bottom toward the nitride center, whereas for hole injection (-FN erase), holes first recombine with the bottom electrons and then gradually move upward. For the electron de-trapping processes under -V(G) stressing, the trapped electrons de-trap first from the bottom portion of nitride. We also develop a method to distinguish the electron de-trapping and hole injection erasing methods by comparing the erasing current density (J) versus the bottom oxide electric field (E). At short-term high-temperature baking, the electrons move from the top portion toward the bottom portion, and this intra-nitride transport becomes more significant for a thicker nitride. On the other hand, after long-term baking, the charge loss mainly comes from the bottom portion of nitride.
An oxide-buffered BE-MANOS charge-trapping device and the role of Al2O3
(2008)
Lai, Sheng-Chih
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Lue, Hang-Ting
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Liao, Chien-Wei
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Huang, Yu-Fong
;
Yang, Ming-Jui
The role of Al2O3 in MANOS device is critically examined, and we conclude that its primary function is to reduce gate injection during erase operation. By itself, Al2O3 cannot stop charge leakage from the charge-trapping nitride layer. Furthermore, Al2O3 provides no magic during the erase operation, and MANOS erases very slowly through charge de-trapping. BE-SONOS [1], with the band engineered ONO tunneling layers, provides efficient channel hole injection for erase. BE-MANOS [2] should be an ideal combination with fast erase and good reliability. However, it shows poor data retention. By inserting a SiO2 buffer layer between Al2O3 and the SiN storage layer, the oxide-buffered BE-MANOS shows good performance and good reliability. The EOT scalability is also investigated.
Highly reliable MA BE-SONOS (Metal-Al2O3 bandgap engineered SONOS) using a SiO2 buffer layer
(2008)
Lai, Sheng-Chih
;
Lue, Hang-Ting
;
Liao, Chien-Wei
;
Wu, Tai-Bor
;
Yang, Ming-Jui
A Metal-high-K Bandgap-Engineered SONOS (MA BE-SONOS) with an additional SiO2 buffer layer is proposed. The thin SiO2 (5 similar to 6 nm) layer between the high-K (Al2O3) and nitride serves to prevent shallow trap generation. Contrary to the previously proposed MANOS or MA BE-SONOS devices using a simple high-k top dielectric, this composite structure eliminates the unstable high-K/nitride interface. Experimental results show that this new device can well suppress the erase saturation, just like MANOS. On the other hand, the data retention is greatly improved, owing to the much more stable interface between the nitride-trapping layer and top oxide. Very large memory window (> 7V) with excellent cycling endurance, read disturb immunity, and data retention has been successfully demonstrated. Theoretical model is also proposed to explain the principle of this device.
Pulse-IV Characterization of Charge-Transient Behavior of SONOS-Type Devices With or Without a Thin Tunnel Oxide
(2009-04-01)
Du, Pei-Ying
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Lue, Hang-Ting
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Wang, Szu-Yu
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Huang, Tiaci-Yuan
;
Hsieh, Kuang-Yeu
The transient behavior of SONOS-type devices was investigated for the first time using pulse-IV technique. Three kinds of SONOS devices are studied: SONS (without top oxide), SONoS (with a thin top oxide), and SoNOS (with a thin bottom oxide). Devices with or without a thin tunnel oxide were able to provide very fast charge injection/detrapping, but their charge-transient behavior cannot be accurately monitored by conventional DC-IV method. By using specific pulse-IV setup for memory, we can measure the drain current response immediately after programming and erasing, as well as the fast charge relaxation under various reliability tests. The program and erase transient behavior shows that all devices are easily programmed and erased within 1 mu s at low gate voltages (< 6 V). Moreover, SONS shows the fastest program and erase speeds because of the absence of tunnel oxide, and silicon nitride has very low barrier height that offers fast injection. We have also examined the charge relaxation under various field and temperature conditions and found that the charge loss mainly came from external charge injection during retention, not from detrapping through thermionic emission.
Reliability Study of MANOS with and without a SiO2 Buffer Layer and BE-MANOS Charge-Trapping NAND Flash Devices
(2009)
Liao, Chien-Wei
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Lai, Sheng-Chih
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Lue, Hang-Ting
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Yang, Ming-Jui
;
Shen, Chin-Yen
The reliability of MANOS devices with an oxide buffer layer (MAONOS) in between SiN trapping layer and high-K Al2O3 top dielectric is extensively studied. We conclude that the primary function of high-K Al2O3 is to suppress the gate electron injection during erase instead of increasing the P/E speed. As a result, inserting a buffer oxide only changes EOT but does not change the P/E mechanisms. On the other hand, the buffer oxide can greatly improve data retention by suppressing leakage through Al2O3. However, owing to the slow erase performances with a thick bottom oxide, both MANOS and MAONOS erase slowly and very high erase voltages must be used. Also, both MANOS and MAONOS devices show very fast endurance degradation below P/E<10, which is inherent due to electron de-trapping mechanism. Moreover, the large erase voltage also causes severe degradation of tunnel oxide after many P/E cycling. To get both speed and reliability performances, it is necessary to introduce bandgap engineered tunneling barrier (BE-MANOS) to solve the fundamental problems of MANOS.
STUDY OF GATE-INJECTION OPERATED SONOS-TYPE DEVICES USING THE GATE-SENSING AND CHANNEL-SENSING (GSCS) METHOD
(2009)
Du, Pei-Ying
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Lue, Hang-Ting
;
Wang, Szu-Yu
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Huang, Tiao-Yuan
;
Hsieh, Kuang-Yeu
SONOS devices using gate injection programming and erasing have better cycling endurance because the gate oxide is not stressed by PIE operations. This work studies the gate injection behavior in detail using the recently developed gate-sensing and channel-sensing (GSCS) technique. GSCS accurately locates the charge centroid during programming/erasing and reliability tests. For the first time, we can track the charge centroid for gate-injection "top BE-SONOS" and various SONOS-type devices. Our results indicate that the charge centroid after electron gate injection is close to the nitride center, irrespective of various nitride thickness and top dielectric. Moreover, there is electron and hole vertical mismatch after hole gate injection. Comparing the results from SONS, we can clearly prove that electrons are mainly distributed inside the bulk nitride instead of the interfaces between oxide and nitride. For SNOS and SNS, where there is electron and hole injection simultaneously, two-region approximation can give us more detailed information about electron and hole capture. By comparing experimental data with theoretical modeling, we have shown that nitride 7nm or thicker captures all the injected electrons up to total charge area density similar to 10(13)cm(-2).
Study of the gate-sensing and channel-sensing transient analysis method for monitoring the charge vertical location of SONOS-type devices
(2007-09-01)
Du, Pei-Ying
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Lue, Hang-Ting
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Wang, Szu-Yu
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Lai, Erh-Kun
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Huang, Tiao-Yuan
The gate-sensing and channel-sensing transient analysis method is studied in detail. This method introduces an additional gate-sensing capacitor to be compared with the conventional channel-sensing one. Sensing in both modes provides two equations that are suitable to solve for two variables-the charge density (Q) and the average charge vertical location (x). In this paper, the principle of this method is discussed in detail. Several factors that affect the measurement accuracy are also analyzed. The power of this method is demonstrated by program/erase cycling and data retention tests. This method is indeed a powerful tool for detailed understanding of trapping dynamics.
Tungsten Oxide Resistive Memory Using Rapid Thermal Oxidation of Tungsten Plugs
(2010)
Lai, Erh-Kun
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Chien, Wei-Chih
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Chen, Yi-Chou
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Hong, Tian-Jue
;
Lin, Yu-Yu
A complementary metal oxide semiconductor (CMOS)-compatible WO(x) based resistive memory has been developed. The WO(x) memory layer is made from rapid thermal oxidation of W plugs. The device performs excellent electrical properties. The switching speed is extremely fast (similar to 2 ns) and the programming voltage (< 1: 4 V) is low. For single-level cell (SLC) operation, the device shows a large resistance window, and 10(8)-cycle endurance. For multi-level cell (MLC) operation, it demonstrates 2-bit/cell storage with the endurance up to 10000 times. The rapid thermal oxidation (RTO) WO(x) resistance random access memory (RRAM) is very promising for both high-density and embedded memory applications. (C) 2010 The Japan Society of Applied Physics