Browsing by Author "Liu, S. L."

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A CMOS-Compatible, High RF Power, Asymmetric-LDD MOSFET with Excellent Linearity
(2008)
Chang, T.
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Kao, H. L.
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Chen, Y. J.
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Liu, S. L.
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McAlister, S. P.
We report the performance of 0.18 mu m RF power MOSFETs with an Asymmetric-Lightly-Doped-Drain (LDD) design. Such devices do not have an n-type drain extension and exhibited better characteristics than conventional MOSFETs at same gate length. The devices showed a DC breakdown voltage of 6.9 V, a 0.54 W/mm power density, 115 GHz f(max), and a good adjacent channel power ratio (ACPR) linearity, as well as a 52% drain efficiency at 2.4 GHz.
Bipolar switching characteristics of low-power Geo resistive memory
(2011-08-01)
Cheng, C. H.
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Chen, P. C.
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Liu, S. L.
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Wu, T. L.
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Hsu, H. H.
We reported an ultra low-power resistive random access memory (RRAM) combining a low-cost Ni electrode and covalent-bond GeO(x) dielectric. This cost-effective Ni/GeO(x)/TaN RRAM device has very small set power of 2 mu W, ultra-low reset power of 130 pW, greater than 1 order of magnitude resistance window, and stable retention at 85 degrees C. The current flow at low-resistance state is governed by Poole-Frenkel conduction with electrons hopping via defect traps, which is quite different from the filament conduction in metal-oxide RRAM. (C) 2011 Elsevier Ltd. All rights reserved.
Low-V(t) TaN/HfLaO n-MOSFETs Using Low-Temperature Formed Source-Drain Junctions
(2009-01-01)
Lin, S. H.
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Liu, S. L.
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Yeh, F. S.
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Chin, Albert
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電子工程學系及電子研究所
We report low-threshold-voltage (V(t)) TaN/HfLaO n-MOSFETs using solid-phase-diffusion (SPD)-formed junctions at a low temperature of 650 degrees C. The gate-first and self-aligned TaN/HflLaO n-MOSFETs using Ni/Sb SPID-formed source-drain junctions showed a low Vt of 0.16 V and a peak electron mobility of 187 cm(2)/V . s at a small 1.3-nm equivalent oxide thickness.
Low-V-t TaN/HfLaO n-MOSFETs Using Low-Temperature Formed Source-Drain Junctions
(2009-01-01)
Lin, S. H.
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Liu, S. L.
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Yeh, F. S.
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Chin, Albert
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電子工程學系及電子研究所
We report low-threshold-voltage (V-t) TaN/HfLaO n-MOSFETs using solid-phase-diffusion (SPD)-formed junctions at a low temperature of 650 degrees C. The gate-first and self-aligned TaN/HflLaO n-MOSFETs using Ni/Sb SPID-formed source-drain junctions showed a low Vt of 0.16 V and a peak electron mobility of 187 cm(2)/V . s at a small 1.3-nm equivalent oxide thickness.
Radio Frequency Power Performance Enhancement for Asymmetric Lightly Doped Drain Metal-Oxide-Semiconductor Field-Effect Transistors on SiC Substrate
(2010)
Chang, Tsu
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Kao, Hsuan-ling
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Liu, S. L.
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Deng, Joseph D. S.
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Horng, K. Y.
In this paper we report the DC characteristics and radio frequency (RF) power performance improvement as high as 6.6% of asymmetric lightly doped drain metal-oxide-semiconductor field-effect transistors (asymmetric LDD MOSFET, AMOSFET) with 50-mu m-thick silicon substrates on SiC substrates. The self-heating and parasitic effects of large size AMOSFETs with 50-mu m-thick silicon on SiC substrates are reduced owing to good heat dissipation and less lossy behaviors of thinned silicon substrates and SiC substrates. Therefore, the power gain, saturation output power, and power added efficiency of AMOSFETs with 50-mu m-thick Si substrates mounted on SiC substrates is improved. (C) 2010 The Japan Society of Applied Physics
The Reliability Study and Device Modeling for p-HEMT Microwave Power Transistors
(2011)
Liu, S. L.
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Chang, H. M.
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Chang, T.
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Kao, H. L.
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Cheng, C. H.
In this paper, the commercial 0.5-mu m AlGaAs/InGaAs/GaAs pseudo-morphic high electron mobility transistors were subjected to both high-drain voltage and high-temperature stresses for investigating reliability issues. The results reveal that the stress-induced trapping phenomena near two-dimensional electron gas layer should be responsible for the different drain current collapses. The decay level of the DC and the small-signal characteristics increases with the stress voltage and/or the operation temperature. The self-consistent model was established through the de-embedded and the non-linear fitting processes, which can be used to estimate the DC and RF small-signal characteristics degradation under high-drain voltage and high-temperature stress.