Browsing by Author "Liu, Shih-Ying"

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An Approach to Anchoring and Placing High Performance Custom Digital Designs
(2015)
Liu, Shih-Ying
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Chen, Tung-Chieh
;
Chen, Hung-Ming
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
Custom layouts of digital blocks are often used in mixed-signal designs in order to meet the critical performance requirements. Unlike traditional standard-cell based digital placement, custom-cell based digital placement may need additional manual help and intervention to achieve higher performance. The need for manual intervention is primarily due to the inability of modern analytical placers in delivering satisfactory performance on placing designs without pre-placed blocks. While most design flow works in a flat or top-down fashion, custom digital design generally works in a bottom-up fashion that there is no prior knowledge on I/O pin plan since it is changeable by the owners of modules. Without any or very few fixed I/O locations, modern analytical placers tend to produce unsatisfactory results. In this work, we propose a method, mimicking the process of making beds, to guide state-of-the-art analytical placers to deliver better placement results. With the crafted pseudo anchors and nets, total HPWL on Capo10.5 [1], mPL6 [2], NTUplace3 [3] and VDAPlace [4] have improved by 2.92%, 8.69%, 25.26% and 10.72% respectively on a set of industry custom digital designs and improved by 2.19%, 4.34%, 36.09%, and 14.27% respectively on Peko-Suite1 benchmarks.
TSV-Based 3D-IC Placement for Timing Optimization
(2011)
Chen, Yi-Rong
;
Chen, Hung-Ming
;
Liu, Shih-Ying
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
The semiconductor technology continue its advnacement in 3D-IC circuit. The concept of 3D-IC introduces additional dimension in latest designs by using stack structures with through-silicon via (TSV). 3D ICs replace long interconnect in 2D ICs with TSV cells. However, optimization in terms of 3D-IC is still immature in many aspects. There still exist problems in placement of standard cells and TSV cells in terms of timing optimization. In this paper, we proposed a methodology on cell placement by applying min-cut partitioning in one layer after layer assignment and address alignment constraint simultaneously. We applied Simulated Annealing to optimize timing and wirelength reduction. In final stage, a greedy legalization procedure is implemented to remove operlaps between cells and TSV cells. Experimental results show that both the wirelengths and the delay of critical paths in 3DICs are much superior compare to 2D ICs.