Browsing by Author "Liu, TM"

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A low-complexity soft VLC decoder using performance modeling
(2004)
Liu, TM
;
Lee, CY
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
In this paper, we propose a scalable soft VLC decoder to greatly reduce overall design complexity. Generally, the soft VLC decoder needs to maintain many states for the correct decoding when the table size grows. We reduce the table size by using a symbol-merging scheme. We merge two symbols with the same prefix into one. Further. to achieve the optimal trade-off between performance and complexity, we propose a Black-Box model. In our model, we present a novel measurement of "symbol-alias" to improve the accuracy of performance estimation. Experimental results show that our scalable soft VLC decoder using performance modeling has more than 1 dB PSNR gain and offers better subjective quality compared to traditional VLC decoding.
A low-power H.264/AVC decoder
(2005)
Lin, TA
;
Liu, TM
;
Lee, CY
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
In this paper, we can save memory access in inter and intra prediction by adopting the proposed memory-efficient decoding ordering. In our proposed hierarchical syntax parser, gated clock technique can be effectively applied to reduce power. Simulation shows the proposed design consumes 88mW in real time decoding 1080HD video sequence.
A memory-efficient deblocking filter for H.264/AVC video coding
(2005)
Liu, TM
;
Lee, WP
;
Lin, TA
;
Lee, CY
;
電子工程學系及電子研究所
A memory-efficient architecture design for de-blocking filter in H.264/AVC is presented. We use the novel data arrangement of Column-of-Pixel to facilitate the memory access and reuse the pixel value. Further, we propose a hybrid filter scheduling to improve the system throughput. As compared with some existing approaches of realizing de-blocking filter [1] [2], the proposed design saves about one-half of processing cycles. With novel data arrangement and hybrid filter scheduling, an efficient architecture design is implemented. Further, it is evaluated on H.264 system and easily achieved real-time decoding with 1080 HD (1920x1088@30fps) when working frequency is 100MHz.
An area-efficient and high-throughput de-blocking filter for multi-standard video applications
(2005)
Liu, TM
;
Lee, WP
;
Lee, CY
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
In this paper, we propose an area-efficient design approach to cover both in-loop and post-loop filtering processes for multiple video coding standards. In addition, we propose a hybrid filter scheduling to improve system throughput. Compared with available designs [1][2], the proposed approach saves about one-half of processing cycles, and hence reduces power dissipation. Compared to the original loop-filter, the proposed loop/post filter only incurs 20.7% of extra cost. Simulation results show that our proposal can easily achieve real-time decoding for 1080HD when the working frequency is 100MHz.
An efficient modeling codec architecture for binary shape coding
(2002)
Liu, TM
;
Shieh, BJ
;
Lee, CY
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
In this paper, the efficient modeling codec architecture for binary shape coding is presented. this novel design includes a memory unit that employs the Address Generation module and the Select & Barrel Shift module to speed up the process of border pixels generation. A simple architecture of the modified modeling unit, which uses a Column-scan map to reduce the number of mux and barrel shifter is proposed. Based on the proposed architecture, it deals with not only context computation of the intra mode but also it of the inter mode on the same hardware architecture. In addition, this design technique is suitable for the context-based arithmetic encode/decode in the whole MPEG4 codec system.
An H.264/AVC decoder with 4x4-block level pipeline
(2005)
Lin, TA
;
Wang, SZ
;
Liu, TM
;
Lee, CY
;
電子工程學系及電子研究所
In this paper, we propose a 4x4-block level pipelining architecture with instantaneous switching scheme and optimal decoding ordering of H.264/AVC decoder. Compared with conventional H.264/AVC video decoders [1)[2], which adopt macroblock level pipelines, our proposed 4x4-block level pipelining architecture of H.264/AVC decoder achieves better hardware utilization. Moreover, our proposed decoding ordering can effectively save memory access and reduce processing cycles, which results in 260,000 MB/s under 100MHZ clock frequency. By adopting these two techniques, our proposed design supports real time decoding with 1080HD (1920x1088) video sequence in 30fps (244,800 MB/s required) and level 4 of baseline profile.