Browsing by Author "Liu, Tsu-Ming"

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A 125 mu W, fully scalable MPEG-2 and H.264/AVC video decoder for mobile applications
(2007-01-01)
Liu, Tsu-Ming
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Lin, Ting-An
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Wang, Sheng-Zen
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Lee, Wen-Ping
;
Yang, Jiun-Yan
A low-power dual-standard video decoder has been developed for mobile applications. It supports MPEG-2 SP@ML and H.264/AVC BL@L4 video decoding in a single chip and features a scalable architecture to reach area/power efficiency. This chip integrates diverse algorithms of MPEG-2 and H.264/AVC to reduce silicon area. Three low-power techniques are proposed. First, a domain-pipelined scalability (DPS) technique is used to optimize the pipelined structure according to the number of processing cycles. Second, bandwidth scalability is implemented via a line-pixel-lookahead (LPL) scheme to improve the external bandwidth and reduce the internal memory size, leading to 51% of memory power reduction compared to a conventional design. Third, low-power motion compensation and deblocking filter are designed to reduce the operating frequency without degrading system performance. A test chip is fabricated in a 0.18 mu m one-poly six=metal CMOS technology with an area of 15.21 mm(2). For mobile applications, H.264/AVC and MPEG-2 video decoding of quarter-common intermediate format (QCIF) sequences at 15 frames per second are achieved at 1.15 MHz clock frequency with power dissipation of 125 mu W and 108 mu W, respectively, at 1 V supply voltage.
A joint architecture of error-concealed deblocking filter for H.264/AVC video transmission
(2007)
Lee, Wen-Ping
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Liu, Tsu-Ming
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Lee, Chen-Yi
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
In this paper, we propose new spatial error concealment (SEC) method, error-concealed de-blocking filter (ECDF), for a real-time decoding system over an error-prone or wireless channel. There are several advantages of ECDF. The first is that ECDF can conceal I frames without the need of flexible macroblock ordering (FMO). Second, the hardware cost of interpolation can be saved. Third, the required information for error concealment (EC) only includes the pixels in the top and left neighbors of current corrupted macroblock (MB). Hence, we can,conceal the corrupted MB without requiring the information in the right and bottom side, leading to the reduction of memory space as well as bandwidth. The implementation results show that the hardware cost of ECDF can be saved about 30% compared to direct implementation. Without the FMO, the proposal gains I.3dB in PSNR compared to bilinear interpolation in JM9.8.
A low-power dual-mode video decoder for mobile applications
(2006-08-01)
Liu, Tsu-Ming
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Lin, Ting-An
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Wang, Sheng-Zen
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Lee, Chen-Yi
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電子工程學系及電子研究所
The objective of this article is to highlight design challenges for low-power and dual-video standard requirements, especially in mobile applications. Due to the advent of the newly announced H.264, a generic problem of standard incompatibility has appeared between H.264 and prevalent MPEG-x video standards, which must be resolved on both algorithmic and architectural levels. Furthermore, several low-power techniques targeted at achieving lower memory requirements and processing cycles are also described and discussed.
A new soft variable length decoder for wireless video transmission
(2007-02-01)
Liu, Tsu-Ming
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Wang, Sheng-Zen
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Shieh, Bai-Jue
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Lee, Chen-Yi
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電子工程學系及電子研究所
In this paper, we propose an adaptive and scalable soft variable length code (VLC) decoder to greatly reduce overall design complexity. Generally, a soft VLC decoder needs to maintain many states for the correct decoding when the sequence length or table size grows. We propose an adaptive sorting scheme to reduce the memory accesses and design complexity. We reduce the table size by using symbol-merging and table-merging schemes. In addition, the proposed Black-Box model improves the accuracy of performance estimation by a novel measurement of "symbol-alias" and also achieves a better tradeoff between performance and complexity. Further, no side information is transmitted and the proposed soft VLC decoder is bandwidth-efficient. The proposed design is evaluated using the model of MPEG-4/UDP-Lite/UEP/AWGN, and hence it is standard-compliant. We averagely improve the peak signal-to-noise ratio by 0.4 similar to 2.9 dB as compared with traditional VLC decoding and standard-support reversible VLC decoding schemes.
A self-grouping and table-merging algorithm for VLC-based video decoding system
(2006)
Sun, Shao-Ming
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Liu, Tsu-Ming
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Lee, Chen-Yi
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
a new VLC-based algorithm for video decoding system is introduced. This Self-grouping algorithm is developed to reduce bit streams needed to decode symbol data. In addition the proposal can be merged with all Huffman table-based VLC systems, such as MPEG-2, H.264, for multi-mode video decoding applications. Simulation results show about 73% in Huffman-based table size can be reduced compared to the state-of-the-art design [9].
An 865-mu W H.264/AVC video decoder for mobile applications
(2005)
Liu, Tsu-Ming
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Lin, Ting-An
;
Wang, Sheng-Zen
;
Lee, Wen-Ping
;
Hou, Kang-Cheng
A low power H.264/AVC video decoder LSI for mobile applications is presented. Video decoding of quarter-common intermediate format (QCIF) sequence at 30 frames per second is achieved at 1.2MHz clock frequency and requires about 865pW at 1.8-V supply voltage. Moreover, CIF, SD and HD sequence format are also supported. The decoder architecture is based on 4x4 sub-block level pipelining that achieves better buffer allocation and decoding throughput. In addition, several modules are designed with new features to improve overall system throughput (up to 260,000 MacroBlock/sec). The proposed solution integrates 456-k logic gates with 161Kb of embedded SRAM in 0.18-mu m single-poly six-metal CMOS process with area of 11.3mm(2).
An improved soft-input CAVLC decoder for mobile communication applications
(2006)
Liu, Tsu-Ming
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Lee, Chen-Yi
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
in this paper, a new CAVLC decoding architecture with a soft-input design concept is proposed. We introduce the soft-decision information to localize the erroneous position at macroblock (MB) levels. Specifically, we compare and select the minimal square difference between the received soft streams and decoded codewords. The corrupted MBs can be early detected and thereby concealed from neighboring pixels. Therefore, more than 1dB of PSNR gain can be achieved under the 2.7x10(-3) of bit error rates.
An in/post-loop deblocking filter with hybrid filtering schedule
(2007-07-01)
Liu, Tsu-Ming
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Lee, Wen-Ping
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Lee, Chen-Yi
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
In this paper, we propose a high-throughput deblocking filter to perform the in-loop or post-loop filtering process for different standard requirements. The performance improvement is very mild if we replace a post-loop filter with an in-loop filter. To alleviate this problem, we derive an integration-oriented algorithm that can be reconfigured as the in-loop or, post-loop filter. Moreover, we develop a hybrid filtering schedule to reach a lower bound of processing cycles. In particular, we reschedule the filtering order and reuse the intermediate pixels when the deblocking filter switches the filtered edges from vertical to horizontal direction. Finally, a 0.18-mu m CMOS design that performs the in/post-loop filter with the hybrid filtering schedule is implemented. The synthesized gate counts are 21.1 K which is reduced to 70% of preliminary design that performs the in-loop or post-loop filter separately. Moreover, it achieves 4 x 10(5) macroblock/s of throughput rate at a 100-MHz clock rate.
Design of a 125 mu W, fully-scalable MPEG-2 and H.264/AVC video decoder for mobile applications
(2006)
Liu, Tsu-Ming
;
Chung, Ching-Che
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Lee, Chen-Yi
;
Lin, Ting-An
;
Wang, Sheng-Zen
A design of MPEG-2 and H.264/AVC video decoder is demonstrated in a 0.18 mu m CMOS [1]. The key design issues involved in this advanced IC are discussed, including improving area and power efficiency. Power dissipation is greatly lowered through the architectural exploration. Measurement results show that MPEG-2 and H.264/AVC real-time decoding of QCIF@15fps are achieved at 1.15MHz with power dissipation of 108 mu W and 125 mu W respectively at 1V supply voltage.
Design of an H.264/AVC decoder with memory hierarchy and line-pixel-lookahead
(2008-01-01)
Liu, Tsu-Ming
;
Lee, Chen-Yi
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This paper describes a novel memory hierarchy and line-pixel-lookahead (LPL) for an H.264/AVC video decoder. The memory system is the bottleneck of most video processors, particularly in the newly announced H.264/AVC. This is because it utilizes the neighboring pixels to create a reliable predictor, leading to a dependency on a long past history of data. This problem can be resolved by allocating memory space but inducing large silicon area and power consumption as well. We first review the existing solutions and propose a three-level memory hierarchy with line-pixel-lookahead to improve access efficiency. Three-level memory hierarchy includes registers, content/slice SRAM and external frame DRAM. We emphasize the need to consider the secondary hierarchy, content/slice SRAM, during the design of an H.264/AVC decoder. Specifically, we introduce a slice SRAM and line-pixel-lookahead to lower the memory capacity and external bandwidth. This SRAM stores neighboring pixels and prevents the data re-access from DRAM. Line-pixel-lookahead exploits multi-dimensional pixel locality so as to averagely improve prediction performance by 6.54% compared to conventional vertical prediction. Simulation results also reveal that the proposal makes a better trade-off between memory allocation and external bandwidth as well as power, leading to 50% of memory power reduction compared to the design without exploiting the secondary slice SRAM hierarchy.
Design of An Intra Predictor with Data Reuse for High-Profile H.264 Applications
(2009)
Lai, Yu-Fan
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Liu, Tsu-Ming
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Li, Yao
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Lee, Chen-Yi
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電子工程學系及電子研究所
This paper presents a high-profile intra predictior for H.264 video decoder. To alleviate the starved bandwidth of intra compensation in high-definition video, we reuse the neighboring pixels and optimize the buffer size and access latency. In particular, a dedicated pixel buffer reuses neighboring pixel for realizing MB-adaptive frame-field (MBAFF) decoding in intra compensation. Moreover, a base-mode predictor is explored to optimize the area efficiency for reference sample filtering process (RSFP) in intra 8x8 modes. Simulation results show that the proposed data-reused intra prediction module requires 14K logic gates and 688 bits SRAM, and operates on 100MHz frequency for realizing 1080HD video playback at 30fps.
Dual-mode high throughput de-blocking filter
(2006-11-23)
Lee, Chen-Yi
;
Liu, Tsu-Ming
This invention provides the unique and high-throughput architecture for multiple video standards. Particularly, we propose a novel scheme to integrate the standard in-loop filter and the informative post-loop filter. Due to the non-standardization of post filter, it provides high freedom to develop a certain suitable algorithm for the integration with loop-filter. We modify the post filter algorithm to make a compromise between hardware integration complexity and performance loss. Further, we propose a hybrid scheduling to reduce the processing cycles and improve the system throughput. The main idea is that we use four pixel buffers to keep the intermediate pixel value and perform the horizontal and vertical filtering process in one hybrid scheduling flow. In our approach, we reduce processing cycles, and the synthesized gate counts are very small. Meanwhile, the synthesized results also indicate lower cost for hardware.
Memory-hierarchy-based power reduction for H.264/AVC video decoder
(2006)
Liu, Tsu-Ming
;
Lee, Chen-Yi
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Memory storage is crucial power factor in H.264/AVC video decoding system. In this paper, we exploit three-level of memory hierarchy to break the data dependency and reduce the number of access for external memory. further, we apply line-pixel-lookahead (LPL) scheme to make a compromise between power consumption and internal memory cost. Experimental results prove that about 50% of memory power reduction can be achieved as compared to comparable decoders without exploiting memory hierarchy [1][2].
Methods for Power/Throughput/Area Optimization of H.264/AVC Decoding
(2010-07-01)
Xu, Ke
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Liu, Tsu-Ming
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Guo, Jiun-In
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Choy, Chiu-Sing
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交大名義發表
This paper presents methods for efficient optimization of ASIC implementation for H.264/AVC video decoding. A systematic approach in optimization is presented in a top-down flow. Tradeoffs among Power, Throughput, and Area (PTA) at both system level and block level are studied and balanced. The system architecture is first evaluated. We then focus on the pipeline organization, parallelism, and memory architecture optimization. Different pipeline granularities are compared and their pros-and-cons are evaluated. Various parallel scenarios, especially 1 x 4-column and 4 x 1-row, are analyzed and compared. Then the detailed designs of various building blocks, such as inverse transform, inter prediction, and deblocking filter, are evaluated and their intrinsic characteristics are exploited to facilitate PTA optimization. Finally, we provide the design guidelines for ASIC implementation based on the analysis and our design experiences of five dedicated decoder chips.