Browsing by Author "Liu, Wei-Chang"

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A 28mW OFDM Baseband Receiver Chip for DVB-T/H with All Digital Synchronization
(2008)
Wei, Ting-Chen
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Liu, Wei-Chang
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Tseng, Chi-Yao
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Long, Syu-Siang
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Jou, Shyh-Jye
An OFDM baseband receiver chip for DVB-T/H application is proposed in this paper. With all-digital jointed detection/synchronization loops and channel estimation, the proposed receiver chip can compensate 200ppm sampling clock offset (SCO) and +/- 50 subcarrier spacing carrier frequency offset (CFO) in multipath environment The total memory requirement of this chip is 102.8KB and the total equivalent gate count (including memory) is about 806,800 gates. By using 0.18 mu m CMOS process, the power consumption is 28mW at 1.45 V, 40MHz and core size of this chip is 3600 mu m x 3600 mu m.
A 3.52 Gb/s mmWave Baseband with Delayed Decision Feedback Sequence Estimation in 40 nm
(2015)
Preyss, Nicholas
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Senning, Christian
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Burg, Andreas
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Liu, Wei-Chang
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Liu, Chun-Yi
We present a digital baseband ASIC for 60 GHz single-carrier (SC) transmission that is optimized for communication scenarios in which most of the energy is concentrated in the first few channel taps. Such scenarios occur for example in office environments with strong reflections. Our circuit targets close-to-optimum maximum-likelihood performance under such conditions. To this end, we show for the first time how a reduced-state-sequence-estimation algorithm can be realized for the 1760 MHz bandwidth of the IEEE 802.11ad standard. The equalizer is complemented in the frontend by a synchronization unit for frequency offset compensation as well as a Golay-sequence based channel estimator and in the backend by an low density parity check (LDPC) decoder. In 40nm CMOS we achieve a measured data rate of up to 3.52 Gb/s using QPSK modulation.
A 40Gb/s All-Digital Adaptive Noise-Suppression Feed-Forward Filter and Adaptive Decision Feedback Equalizer with 40 parallelisms for 2-PAM Systems
(2018-01-01)
Ng, Chee-Kit
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Lin, Yu-Chun
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Liu, Wei-Chang
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Wu, Chin-Feng
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Lou, Shyh-Lye
A 40Gb/s all-digital adaptive noise-suppression feed-forward filter/equalizer (AFFE) and adaptive decision feedback equalizer (ADFE) for 2-level pulse amplitude modulation (2-PAM) systems is presented. Batch mode coefficients update (BMCU) unit together with coefficients-Iookahead scheme are proposed to achieve high parallelism architecture for ADFE. With these schemes, new extended incremental coefficients-Iookahead filter architecture is proposed to provide high throughput rate and to reduce hardware complexity of parallel ADFE. Besides, feed-forward noise-suppression architecture is proposed for AFFE to provide better signal-to-noise ratio (SNR). The equalizer operates at 1 GHz system clock with 40 parallelisms is implemented in 40nm CMOS technology with a core area 0.23mm(2). The measurement results verify the equalizer performance and the maximum throughput of 40Gb/s is achieved under 0.9V supply with 4.35pJ/bit energy efficiency.
A 802.15.3c/802.11ad Compliant 24 Gb/s FFT Processor for 60 GHz Communication Systems
(2015)
Davila, Henry Lopez
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Liu, Chun-Yi
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Liu, Wei-Chang
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Huang, Shen-Jui
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Jou, Shyh-Jye
This paper, we present a 24 Gb/s 512-point 8X-parallel FFT processor for 60 GHz communication systems. The proposed design is a pipelined Multipath Delay Feedback (MDF) radix-2(3) architecture, which exploits the parallelism of the multipath scheme together with pipeline technique to achieve a high throughput rate. Besides, the proposed FFT processor is implemented with an area efficient optimized multiplier architecture that avoid the need to store the twiddle factor in memory and a dynamic scaling technique to enhance the SQNR, allowing the FFT to operate with 16-QAM and 64-QAM for single carrier (SC) and orthogonal frequency-division multiplexing(OFDM) schemes. This FFT processor has been implemented in a SC/OFDM dual-mode baseband receiver satisfying the requirements of the 802.15.3c/802.11ad standard with a 40nm CMOS process. The post-layout implementation results show that the proposed FFT processor is able to achieve up to 24 Gb/s throughput rate at 500MHz clock with a power consumption of 87mW and area of 0.64mm(2).
A 802.15.3c/802.11ad Dual Mode Phase Noise Cancellation for 60 GHz Communication Systems
(2015)
Huang, Liang-Yu
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Wu, Chia-Yi
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Liu, Chun-Yi
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Liu, Wei-Chang
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Wu, Chih-Feng
In this paper, a phase noise cancellation (PNC) architecture is presented for 60 GHz communication systems. The BER performance is severely degraded by the non-ideal carrier frequency in 60 GHz bandwidth, which causes both common phase error (CPE) and residual carrier frequency offset (RCFO). The proposed simplified two-stage CPE algorithm solves the RCFO and common phase nose in the frequency domain and eliminates the constellation rotation on each sub-channel. Two-stage architecture together with deep pipelining technique achieves a high throughput rate. This PNC architecture has been implemented in a SC/OFDM Dual-Mode baseband receiver satisfying the requirements of the 802.15.3c/802.11ad standard with a 40 nm process. The proposed PNC is able to support 64QAM/16QAM for OFDM/SC mode, and can achieve up to 19.2 Giga-hit per second (Gbps) throughput rate at 400 MHz operating frequency with power consumption of 33 mW and area of 0.142 mm(2).
A Digital Golay-MPIC Time Domain Equalizer for SC/OFDM Dual-Modes at 60 GHz Band
(2013-10-01)
Liu, Wei-Chang
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Yeh, Fu-Chun
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Wei, Ting-Chen
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Chan, Ching-Da
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Jou, Shyh-Jye
In this paper, a digital time domain equalizer (TDE) for 60 GHz radio frequency transmission systems is presented. Significantly, the TDE supports both single carrier (SC) and orthogonal frequency-division multiplexing (OFDM) operation modes for digital baseband receiver. In order to improve the performance, the proposed TDE adopts Golay sequence aided one-shot channel estimation and modified multi-path interference cancellation (MPIC) equalization. Targeting on the line-of-sight (LOS) channel characteristic, MPIC is simplified with single-tap for complexity reduction. From the area efficiency point of view, both SC and OFDM modes are designed within a single hardware to yield 99% of area sharing. The Golay-MPIC TDE structure is realized as feed-forward data path with 8X-parallelism to achieve 2.64 GS/s at 330 MHz clock rate. The Golay-MPIC TDE is fabricated as a part of a digital baseband with 65 nm 1P9M general purpose process. The area of Golay-MPIC TDE occupies 1.05 with 405 K gate counts. Besides, the power dissipations for SC and ODFM modes are 56.71 mW@220 MHz (1 V) and 91.29 mW@330 MHz (1.1 V), respectively. Finally, the chip can provide the maximum throughput 15.84 Gb/s (2.64 GS/s with 64-QAM modulation).
A jointed mode detection and symbol detection scheme for DVB-T
(2008-05-01)
Wei, Ting-Chen
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Liu, Wei-Chang
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Jou, Shyh-Jye
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
This work proposes a jointed mode detection and symbol detection scheme for DVB-T To reduce hardware complexity, the division operation of normalized maximum correlation (NMC) is removed and the delay line which uses twisted memory access method lowers the hardware cost. In addition, the proposed detection procedure does not need to refill or replenish the received data samples; as the result, the longest latency of the detection is only 17280 samples and is comparable with the parallel method. To lower the hardware cost, the memory is released for channel estimation after completing the Mode/GI detection and symbol detection. Total complexity of Mode/GI/symbol detection and channel estimation is about 200 Kgates (including memory)(1).
A Micro-Network on Chip with 10-Gb/s Transmission Link
(2009)
Liu, Wei-Chang
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Lin, Chih-Hsien
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Jou, Shyh-Jye
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Lu, Hung-Wen
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Su, Chau-Chin
In this paper, a micro-network on chip (MNoC) with 10-Gb/s transmission link is proposed. A prototype system with two 5-port packet-based on-chip micro-switches and a 10-Gb/s data transceiver with an all digital data recovery circuit and a self-calibration clock generator are designed. This chip is implemented in 0.13 mu m CMOS technology. The core area of this chip is 990 mu m*1600 mu m and the power consumption is 155mW (60mW for micro-switches and 95mW for 10-Gb/s data transceiver) at 1.2V supply voltage with 10-Gb/s transmission data rate.
A SC/HSI Dual-Mode Baseband Receiver with Frequency-Domain Equalizer for IEEE 802.15.3c
(2013)
Liu, Wei-Chang
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Yeh, Fu-Chun
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Wei, Ting-Chen
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Huang, Ya-Shiue
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Liu, Tai-Yang
In this paper, an 8X-parallelism digital baseband receiver is proposed for IEEE 802.15.3c application. The baseband receiver consists of all-digital synchronization, radix-16 FFT and LS-LMS equalizer modules. It supports SC and HSI dual-mode in IEEE 802.15.3c with single hardware for area efficiency. The chip is implemented with 65 nm 1P9M process. The fabricated area is 12.96 mm(2) with 3463 K gate counts. The post-layout verification shows the throughput rate under QPSK modulation achieves 3.52 Gb/s and 5.28 Gb/s for SC mode (220 MHz) and HSI mode (330 MHz), respectively.
A SC/OFDM Dual Mode Frequency-Domain Equalizer for 60GHz Multi-Gbps Wireless Transmission
(2011)
Yeh, Fu-Chun
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Liu, Tai-Yang
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Wei, Ting-Chen
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Liu, Wei-Chang
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Jou, Shyh-Jye
This work proposes an adaptive frequency-domain equalizer (FDE) for single carrier and OFDM indoor over Gbps data rate wireless receiver. System simulation and specifications are based on the IEEE 802.15.3c standard. The proposed LS-LMS FDE uses low computational complexity Least-Mean-Square (LMS) algorithm with Least-Square (LS) channel estimation to accelerate the convergence speed. The FDE can be used for dual mode (SC and HSI) Wireless Personal Area Networks (WPAN) system. The simulation results show that the LS-LMS FDE can achieve 1.32*10(-4) BER in SC mode and 6.55*10(-3) in HSI mode (both uncoded) at SNR 14 dB. The total area is about 415K gate-count with 69% shared among single carrier and OFDM mode except 2 FFT. The power consumption is only 81.27 mW when working at 400MHz.
All-Digital Synchronization for SC/OFDM Mode of IEEE 802.15.3c and IEEE 802.11ad
(2015-02-01)
Liu, Wei-Chang
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Wei, Ting-Chen
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Huang, Ya-Shiue
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Chan, Ching-Da
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Jou, Shyh-Jye
In this paper, a detection and estimation scheme and its architecture design for synchronization in 60 GHz indoor wireless transmission are presented. With the complementary Golay sequence based preamble structure, the proposed synchronization scheme is designed to detect the preamble and symbol boundary, estimate the frequency offset within a unified architecture. For the very high sampling speed at 60 GHz transmission, the architecture is designed as 8x-parallelism with feed-forward data path. This architecture supports the single carrier (SC) and orthogonal frequency-division multiplexing (OFDM) transmissions of both IEEE 802.15.3c and IEEE 802.11ad standards. The synchronization module is implemented as a part of a digital baseband receiver for IEEE 802.15.3c. The tolerance of maximum frequency offset is about 114.58 ppm and 171.87 ppm for SC and OFDM mode, respectively. The implementation result shows that it takes about 0.84 mm(2) of area (equivalent to 307 k gate counts). The power consumption is about 59 mW in SC mode and 96 mW in OFDM (HSI) mode when operating at 1.76 GHz and 2.64 GHz chip rate, respectively.
An 8X-Parallelism Memory Access Reordering Polyphase Network for 60 GHz FBMC-OQAM Baseband Receiver
(2016-12-01)
Liu, Chun-Yi
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Sie, Meng-Siou
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Leong, Edmund Wen Jen
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Yao, Yu-Cheng
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Lopez, Henry
Filter bank multi-carrier (FBMC) is a kind of new waveform that is an important topic in 5th generation wireless systems (5G). In this paper, we propose a novel memory access reordering polyphase network (PPN) for FBMC offset QAM (OQAM) system at 60 GHz band. The novel PPN architecture has lower complexity than the state-of-the-art designs, and it can be used in any FBMC-OQAM baseband design. To evaluate the system performance and hardware complexity of baseband receiver in millimeter wave (mmW) band, the proposed PPN is integrated into our 8X-parallelism 60 GHz band baseband receiver. The out-of-band (OOB) radiation in fixed-point simulation has 25 dB improvement as compared with OFDM. Furthermore, the transmission efficiency of FBMC-OQAM baseband receiver can improve 52% due to using more data subcarriers and removal of cyclic prefix (CP). The proposed PPN is synthesized with 40 nm 1P9M general purposes (GP) process, and can operate at 330/500 MHz clock rate with power consumption of 17/26 mW, providing the maximum PHY data rate up to 21.4 Gb/s.
An 8X-Parallelism Memory Access Reordering Polyphase Network for 60 GHz FBMC-OQAM Baseband Receiver
(2016-12)
Liu, Chun-Yi
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Sie, Meng-Siou
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Leong, Edmund Wen Jen
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Yao, Yu-Cheng
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Lopez, Henry
Filter bank multi-carrier (FBMC) is a kind of new waveform that is an important topic in 5th generation wireless systems (5G). In this paper, we propose a novel memory access reordering polyphase network (PPN) for FBMC offset QAM (OQAM) system at 60 GHz band. The novel PPN architecture has lower complexity than the state-of-the-art designs, and it can be used in any FBMC-OQAM baseband design. To evaluate the system performance and hardware complexity of baseband receiver in millimeter wave (mmW) band, the proposed PPN is integrated into our 8X-parallelism 60 GHz band baseband receiver. The out-of-band (OOB) radiation in fixed-point simulation has 25 dB improvement as compared with OFDM. Furthermore, the transmission efficiency of FBMC-OQAM baseband receiver can improve 52% due to using more data subcarriers and removal of cyclic prefix (CP). The proposed PPN is synthesized with 40 nm 1P9M general purposes (GP) process, and can operate at 330/500 MHz clock rate with power consumption of 17/26 mW, providing the maximum PHY data rate up to 21.4 Gb/s.
An IEEE 802.15.3c/802.11ad Compliant SC/OFDM Dual-Mode Baseband Receiver for 60 GHz Band
(2014-01-01)
Liu, Wei-Chang
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Yeh, Fu-Chun
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Wu, Chia-Yi
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Wei, Ting-Chen
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Huang, Ya-Shiue
In this paper, a dual-standard, dual-mode baseband receiver for 60 GHz wireless communication is presented. The receiver is designed to support SC and OFDM modes for both IEEE 802.15.3c and IEEE 802.11ad standards. The receiver is integrated with all-digital synchronization, radix-16 FFT, phase noise cancellation and low-complexity time-domain equalizer for line-of-sight channel application. The hardware utilization achieves 70% by leveraging hardware sharing between two modes and two standards for area efficiency. The receiver is implemented with 65 nm 1P9M process in 7.95 mm(2) core area. With feed-through architecture, the throughput rate supports up to 7.04 Gb/s and 15.84 Gb/s for SC mode (220 MHz) and OFDM mode (330 MHz), respectively.
Blind mode/GI detection and coarse symbol synchronization for DVB-T/H
(2007)
Liu, Wei-Chang
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Wei, Ting-Chen
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Jou, Shyh-Jye
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
In a Non-Data-Aided (NDA) broadcasting system such as DVB-T/H, blind transmission mode, guard interval (GI) length detection and coarse symbol synchronization (CSS) play important roles to estimate the transmitted OFDM symbol parameters and start the synchronization processes. In this paper, a single hardware and division-free architecture, modified from Normalized-Maximum-Correlation (NMC) architecture, for DVB-T/H blind mode/GI detection and coarse symbol synchronization (CSS) is proposed. By adopting the proposed twister memory access scheme and sequential blind mode detection scheme, the architecture reduces 33% of memory costs and at most 58.18% mode detection latencies.
Design and Implementation of Synchronization Detection for IEEE 802.15.3c
(2011)
Huang, Ya-Shiue
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Liu, Wei-Chang
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Jou, Shyh-Jye
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
In this paper, a jointed preamble/boundary detection and fractional carrier frequency offset (CFO) estimation design is presented which supports dual SC/HSI modes of IEEE 802.15.3c applications. Based on correlation based algorithms which utilizes the structure of preamble, an efficiency architecture is proposed which realizes synchronization detection with a sequential detection scheme and only single hardware for dual modes and three detection operations. In order to achieve the requirement of sampling rate, the architecture is 8x parallelism and operates at 330 MHz clock rate. The total gate count is 189k in 65 nm 1P9M CMOS process with power consumption of 60.16 mW including memory elements which occupies 63.26 % and can be shared with the frequency domain equalizer (FDE).
Dual-Mode All-Digital Baseband Receiver With a Feed-Forward and Shared-Memory Architecture for Dual-Standard Over 60 GHz NLOS Channel
(2017-03-01)
Liu, Chun-Yi
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Sie, Meng-Siou
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Leong, Edmund Wen Jen
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Yao, Yu-Cheng
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Jen, Chih-Wei
In this paper, an 8X-parallelism all-digital baseband receiver is proposed to support SC and OFDM modes for both IEEE 802.15.3c and IEEE 802.11ad standards. The all-digital baseband receiver contains a 4-in-1 synchronization (SYNC), a 512-point radix-23 IFFT/FFT, a phase noise cancellation (PNC), a shared memory (MEM) bank and a frequency-domain equalizer (FDE) with an optimized golay-correlator window-based noise cancellation (OGC-WNC) channel estimation (CE) for non-line-of-sight (NLOS) and line-of-sight (LOS) channels. The hardware sharing is 99% between SC and OFDM modes and the shared memory reduces memory usage by 51%. The measurement results show that the fabricated chip can provide PHY data rate of 9.24 Gb/s with power consumption of 497 mW to meet the requirement of OFDM mode for IEEE 802.15.3c and 802.11ad standards. Besides, the PHY data rate of the fabricated chip reaches 14 Gb/s with power consumption of 698 mW for OFDM mode that is beyond the standard requirement to offer higher PHY data rate over 60 GHz transmission environment.
ERROR-RESILIENT SEQUENTIAL CELLS WITH SUCCESSIVE TIME BORROWING FOR STOCHASTIC COMPUTING
(2016)
Liu, Wei-Chang
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Chan, Ching-Da
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Huang, Shuo-An
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Lo, Chi-Wei
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Yang, Chia-Hsiang
This paper presents error-resilient sequential building blocks with time-borrowing capability without extra latches and generated clocks. The circuits are able to recover the timing errors caused by PVT variations and/or over-voltage scaling by up to half a cycle. Unlike prior works, the timing errors can be recovered dynamically through successive time borrowing without stalled cycles, retaining a constant throughput. The circuit structure can be applied to both ASICs and microprocessors. The proposed sequential cells are highly compatible with current cell-based IC design flow, for both feed-forward and feedback datapaths. As a proof of concept, a design with key DSP building blocks has been verified. The results show that the performance of the DSP modules is improved by 13-15% in the worst-case operation condition, yielding a promising solution for stochastic computing under an unreliable operation condition.
Gb/s Prototyping of 60GHz Indoor Wireless SC/OFDM Transmitter and Receiver on FPGA Demo System
(2015)
Arya, Pranav
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Huang, Liang-Yu
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Liu, Wei-Chang
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Chang, Hsin-Ting
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Jen, Chih-Wei
This work presents a dual mode, single carrier (SC) and high speed interface (HSI), wireless baseband receiver which implements the IEEE standards 802.15.3c 111 and 802.11.ad [2]. The proposed architecture of the baseband receive is designed as 8 parallelism with feed-forward data path reducing the operating frequency and can achieve high throughput for indoor communication. Besides, our goal is to demonstrate the system on Xilinx VC707 FPGA evaluation board and achieve multi-Gb/s data speed and low bit error rate (BER). The data rates achieved by the prototype are 1.5 Gb/s and 4.5 Gb/s for QPSK and 64QAM data in HSI mode, respectively. The specified (BER) of 10(-2) has been achieved for QPSK and 64QAM data at 8.3dB and 22.6dB, respectively.
Golay-Correlator Window-Based Noise Cancellation Equalization Technique for 60-GHz Wireless OFDM/SC Receiver
(2016-11)
Wu, Chih-Feng
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Liu, Wei-Chang
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Tsui, Chia-Chun
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Liu, Chun-Yi
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Sie, Meng-Siou
In this paper, a Golay-correlator window-based noise cancellation (GC-WNC) technique with frequency-domain equalizer (FDE) is proposed. The GC-WNC is a cooperative scheme in the time and frequency domains to combat the multipath effect in nonline-of-sight (NLOS) and LOS channels for orthogonal frequency-division multiplexing (OFDM) and single-carrier mode baseband inner receiver over 60-GHz environment for IEEE 802.15.3c and 802.11ad. According to mean-square error criterion, WNC approach is to minimize the estimation error between the ideal and the estimated channel frequency response (CFR) on each subchannel. The CFR is precisely obtained as coefficients of FDE to compensate multipath effect even in NLOS channel. The GC-WNC FDE with 8X-parallelism is designed as a part of digital baseband inner receiver with 40-nm CMOS general-purpose process. Because of area restriction of tape-out chip, only the OFDM mode is fabricated in the chip. The GC-WNC FDE has an equivalent gate count of 230k occupying 11.3% of the baseband inner receiver. Based on the chip measurement results, the baseband inner receiver with GC-WNC FDE provides 24-Gb/s throughput with 500-MHz operating clock and 0.94 V supply voltage. The power consumption of GC-WNC FDE is 69.79 mW. The baseband inner receiver with GC-WNC FDE can deliver a multigigabit per second throughput with the power dissipation of 2.91/2.26 mW/Gb/s at 500-/330-MHz operating clock for the OFDM mode.