Browsing by Author "Liu, Wentai"

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A Fully Integrated Wireless SoC for Motor Function Recovery After Spinal Cord Injury
(2017-06-01)
Lo, Yi-Kai
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Kuan, Yen-Cheng
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Culaclii, Stanislav
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Kim, Brian
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Wang, Po-Min
This paper presents a wirelessly powered, fully integrated system-on-a-chip (SoC) supporting 160-channel stimulation, 16-channel recording, and 48-channel bio-impedance characterization to enable partialmotor function recovery through epidural spinal cord electrical stimulation. A wireless transceiver is designed to support quasi full-duplex data telemetry at a data rate of 2 Mb/s. Furthermore, a unique in situ bio-impedance characterization scheme based on time-domain analysis is implemented to derive the Randles cell electrode model of the electrode-electrolyte interface. The SoC supports concurrent stimulation and recording while the high-density stimulator array meets an output compliance voltage of up to +/- 10 V with versatile stimulus programmability. The SoC consumes 18 mW and occupies a chip area of 5.7 mm x 4.4 mm using 0.18 mu m high-voltage CMOS process. In our in vivo rodent experiment, the SoC is used to perform wireless recording of EMG responses while stimulation is applied to enable the standing and stepping of a paralyzed rat. To facilitate the system integration, a novel thin film polymer packaging technique is developed to provide a heterogeneous integration of the SoC, coils, discrete components, and high-density flexible electrode array, resulting in a miniaturized prototype implant with a weight and form factor of 0.7 g and 0.5 cm(3), respectively.
Circuit and Coil Design for In-Vitro Magnetic Neural Stimulation Systems
(2009-10-01)
Basham, Eric
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Yang, Zhi
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Liu, Wentai
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交大名義發表
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National Chiao Tung University
Magnetic stimulation of neural tissue is an attractive technology because neural excitation may be affected without requiring implantation of electrodes. Pulsed discharge circuits are typically implemented for clinical magnetic stimulation systems. However, pulsed discharge systems can confound in-vitro experimentation. As an alternative to pulsed discharge circuits, we present a circuit to deliver asymmetric current pulses for generation of the magnetic field. We scaled the system down by using ferrite cores for the excitation coil. The scaled system allows observation using electrophysiological techniques and preparations not commonly used for investigation of magnetic stimulation. The design was refined using a comprehensive set of design equations. Circuit modeling and simulation demonstrate that the proposed system is effective for stimulating neural tissue with electric-field gradients generated by time-varying magnetic fields. System performance is verified through electrical test.
NEUSORT2.0: A Multiple-channel Neural Signal Processor with Systolic Array Buffer and Channel-interleaving Processing Schedule
(2008)
Chen, Tung-Chien
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Yang, Zhi
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Liu, Wentai
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Chen, Liang-Gee
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交大名義發表
An emerging class of neuroprosthetic devices aims to provide aggressive performance by integrating more complicated signal processing hardware into the neural recording: system with a large amount of electrodes. However, the traditional parallel structure duplicating one neural signal processor (NSP) multiple times for multiple channels takes a heavy burden on chip area. The serial structure sequentially switching the processing task between channels requires a bulky memory to store neural data and may has a long processing delay. In this paper, a memory hierarchy of systolic array buffer is proposed to support signal processing interleavingly channel by channel in cycle basis to match up with the data flow of the optimized multiple-channel frontend interface circuitry. The NSP can thus be tightly coupled to the analog frontend interface circuitry and perform signal processing for multiple channels in real time without any bulky memory. Based on our previous one-channel NSP of NFUSORT1.0 [1], the proposed memory hierarchy is realized on NFUSORT2.0 for a 16-channel neural recording system. Compared to 16 of NEUSORT1.0, NEUSORT2.0 demonstrates a 81.50% saving in terms of area x power factor.
VLSI Architecture of Leading Eigenvector Generation for On-chip Principal Component Analysis Spike Sorting System
(2008)
Chen, Tung-Chien
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Liu, Wentai
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Chen, Liang-Gee
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交大名義發表
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National Chiao Tung University
On-chip spike detection and principal component analysis (PCA) sorting hardware in an integrated multi-channel neural recording system is highly desired to ease the bandwidth bottleneck from high-density microelectrode array implanted in the cortex. In this paper, we propose the first leading eigenvector generator, the key hardware module of PCA, to enable the whole framework. Based on the iterative eigenvector distilling algorithm, the proposed flipped structure enables the low cost and low power implementation by discarding the division and square root hardware units. Further, the proposed adaptive level shifting scheme optimizes the accuracy and area trade off by dynamically increasing the quantization parameter according to the signal level. With the specification of four principal components/channel, 32 samples/spike, and nine bits/sample, the proposed hardware can train 312 channels per minute with 1MHz operation frequency. 0.13 mm(2) silicon area and 282 mu W power consumption are required in 90 nm 1P9M CMOS process.