Browsing by Author "Liu, Yen-Lin"

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A 0.6-V 0.33-mW 5.5-GHz Receiver Front-End Using Resonator Coupling Technique
(2011-06-01)
Li, Chun-Hsing
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Liu, Yen-Lin
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Kuo, Chien-Nan
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
In this study, a low-power and low-voltage 5.5-GHz receiver front-end circuit is designed using a resonator coupling technique. An on-chip transformer combined with the parasitic capacitances from a low-noise amplifier (LNA), a mixer, and the transformer itself comprises two coupled resonators of the resonator coupling network (RCN). The RCN functions as a balun, and couples energy from the LNA to the mixer. Under the critical coupling condition, the RCN gives a maximal current gain at resonance frequencies, equivalent to the same level by an ideal transformer. The analysis shows that the current gain is quite tolerable to the coupling coefficient variation, an advantageous feature for on-chip transformer design. The technique is verified by the receiver front-end in 0.18-mu m CMOS technology. The RCN possess a current gain as high as 12 dB at 5.5 GHz. The measured input return loss, conversion gain, and third-order intermodulation intercept point of the entire circuit are 16 dB, 17.4 dB, and -1.5 dBm, respectively. The noise figure is 7.8 dB at the IF frequency of 1 MHz. The power consumption is only 0.33 mW from a 0.6-V supply. The required local oscillator power is only -9.5 dBm. This receiver front-end successfully demonstrates the resonator coupling technique.
Low Voltage Low Power 5-GHz Double-Balanced Mixer with Active Phase Splitter
(2010-01-01)
Liu, Yen-Lin
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Li, Chun-Hsing
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Kuo, Chien-Nan
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
In this work a low-power double-balanced mixer is designed to operate at 5-GHz. The circuit topology is chosen available for low supply voltage below 1 V. The mixer consists of a transconductance stage and PMOS switching pairs in a folded topology. Phase splitting function is integrated in the transconductance stage, composed of a common-gate and a common-source transistors. Output balance condition and noise performance of the transconductance stage are analyzed. Realized in 0.18-um CMOS technology, the measured input return loss and voltage conversion gain are 11 dB and 10.4 dB, respectively. The input third-order intercept point (IIP3) is 3.8 dBm while consuming only 2 mW from supply voltage of 1 V.
Sub-nW 5-GHz receiver front-end circuit design
(2007)
Hsu, Tatao
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Liu, Yen-Lin
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Yen, Shu-Hui
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Kuo, Chien-Nan
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交大名義發表
In this work a 5-GHz receiver front-end is designed for the application of wireless sensor networks. The circuit topology is chosen available for low supply voltage below 1V The stability condition of the LNA circuit is ensured by adding reactive components. Total power consumption of the fabricated circuit is 0.86mW, of which 0.7mW goes to the LNA stage. The measured return loss and conversion gain are 11dB and 25dB, respectively. The noise figure is 12dB and the IIP3 is around -6.5dBm.