Browsing by Author "Liu, You-Sheng"

Now showing 1 - 3 of 3

A Statistical Model for the Headed and Tail Distributions of Random Telegraph Signal Magnitudes in Nanoscale MOSFETs
(2014-07-01)
Chen, Ming-Jer
;
Tu, Kong-Chiang
;
Wang, Huan-Hsiung
;
Chen, Chuan-Li
;
Lai, Shiou-Yi
Trapping-detrapping of a single electron via an individual trap in metal-oxide-semiconductor field-effect transistor (MOSFET) gate dielectric constitutes two-level random telegraph signals. Recent 3-D technology computer-aided design (TCAD) simulations, on an individual MOSFET, revealed that with the position of the trap as a random variable, resulting random telegraph signals relative magnitude Delta I-d/I-d in the subthreshold current at low drain voltage can have two distinct distributions: a headed one for a percolation-free channel and a tail one for a percolative channel. The latter may be effectively treated by a literature formula: (Delta I-d/I-d) = (I-loc/I-d)(2), where I-loc is the local current around the trap. In this paper, we show how to make this formula practically useful. First, we conduct 3-D TCAD simulations on a 35 x 35-nm(2) channel to provide Delta I-d/I-d for a few positions of the trap. This leads to a new statistical model in closed form, which can reproduce headed distributions. Straightforwardly, key criteria are drawn from the model, which can act as guidelines for the adequate use of the I-loc/I-d formula. Extension to threshold voltage shift counterparts, from subthreshold through transition to inversion, is successfully achieved. Importantly, use of the model may overcome the drawbacks of the statistical experiment or simulation in the field.
Investigation of Ferroelectric Granularity for Double-Gate Negative-Capacitance FETs Considering Position and Number Fluctuations
(2019-01-01)
Fan, Che-Lun
;
Tseng, Kuei-Yang
;
Liu, You-Sheng
;
Su, Pin
;
電子工程學系及電子研究所
Using TCAD atomistic simulation, this work investigates the ferroelectric layer granularity of double-gate (DG) negative-capacitance FETs (NCFET) by considering both position and number fluctuations. Our study indicates that the impacts of the ferroelectric ratio on threshold voltage (V-T) and subthreshold swing (SS) variations exhibit non-monotonic characteristics, and it is important to include the number fluctuation of the ferroelectric grain to accurately account for the overall variation. In addition, smaller grain size not only reduces the V-T and SS variations, but also improves the mean value of the subthreshold swing.
Variability Analysis for Ferroelectric FET Nonvolatile Memories Considering Random Ferroelectric-Dielectric Phase Distribution
(2020-03-01)
Liu, You-Sheng
;
Su, Pin
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This paper investigates the impact of the random ferroelectric-dielectric (FE-DE) phase distribution on the memory window (MW) of the ferroelectric field-effect transistor (FeFET) nonvolatile memory (NVM) with the aid of TCAD atomistic simulations. Our study indicates that the DE path from source to drain is detrimental to the MW, and down-scaling the gate length substantially increases the probability of forming DE path and the variability in the MW. In addition, the MW variability for scaled FeFET devices can be mitigated by reducing the grain size, even under the same grain-to-channel area ratio. Besides, when down-scaling the insulator thickness to increase the MW, the increased MW variability due to the random FE-DE grains needs to be considered. Our study may provide insights for future scaling of FeFET NVMs.