Browsing by Author "Liu, Yu-Wei"

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Derivations of Factors Influencing the Technology Acceptance of Smart TV by Using the DEMATEL Based Network Process
(2012)
Huang, Chi-Yo
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Liu, Yu-Wei
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Tzeng, Gwo-Hshiung
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科技管理研究所
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Institute of Management of Technology
Information technology (IT) products have played significant roles from both aspects of market development as well as technology growth. However, predicting technology acceptance toward the IT products is always challenging for marketers and designers. Also, the characteristics of and strategies for IT products at different stages of product life cycle are different. Therefore, the customers\' preference and needs change rapidly at different stages in product life cycle. However, very few scholars tried to explore how the technology can be accepted at various stages of a product life cycle was seldom discussed. But the issue is very important. Thus, this research aims to propose DEMATEL based Network Process for discovering the influential factors of the technology acceptance for introduction stage IT product. An empirical study based on the Smart TV for introduction stage will be used to verify the feasibility of this framework. Further, the Lead User Method will be applied to predict the preference and the purchase behavior of mass user and the result could be a reference for industrial marketing activities and design process.
Investigation of Pillar-Concave Structure for Low-Temperature Cu-Cu Direct Bonding in 3-D/2.5-D Heterogeneous Integration
(2020-08-01)
Chou, Tzu-Chieh
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Yang, Kai-Ming
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Li, Jian-Chen
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Yu, Ting-Yang
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Yang, Yu-Tao
With the advantage of high surface-roughness tolerance, the pillar-concave Cu-Cu direct bonding without chemical-mechanical planarization (CMP) is investigated in detail, including the mechanism of thermal compensation, analysis of roughness, bonding strength, and bonding reliability. With the special design of Cu bond structure, excellent bonding results can be achieved under low thermal budget (150 degrees C for 1 min, atmosphere) with even high roughness of bonding surface. In addition, the pillar-concave scheme applied to fan-out panel-level package (FOPLP) has been demonstrated, showing the high feasibility of this scheme to realize applications in heterogeneous integration.
Monolithic 3D BEOL FinFET switch arrays using location-controlled-grain technique in voltage regulator with better FOM than 2D regulators
(2019-01-01)
Hsieh, Ping-Yi
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Chang, Yi-Jui
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Chen, Pin-Jun
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Chen, Chun-Liang
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Yang, Chih-Chao
Monolithic 3D back-end of line (BEOL) FinFET switch arrays are demonstrated in large single crystalline Si islands (2.56 mu m(2)), whose location, size and shape are determined by design. Details of the improved location-controlled-grain (LCG) technique are presented. A voltage regulator implemented with the BEOL switch arrays using external control signals shows better theoretical figure of merit (FOM) of 0.089ns than 2D voltage regulators of 0.43ns.