Browsing by Author "Lo, Chi-Hsiang"

Now showing 1 - 2 of 2

A-68.5 dB IM3 Low-Voltage CMOS Transconductor with Wide Tuning Range
(2010-08-01)
Lo, Tien-Yu
;
Hung, Chung-Chih
;
Lo, Chi-Hsiang
;
電機工程學系
;
Department of Electrical and Computer Engineering
A CMOS transconductor for multi-mode application is presented. The transconductor includes a voltage-to-current converter and a current multiplier. Voltage-to-current conversion employs linear region MOS transistors, and the conversion features high linearity over a wide input swing range. The current multiplier, which operates in the weak inversion region, provides a wide transconductance tuning range without degrading the linearity. The transconductor was designed and fabricated in the TSMC 0.18-mu m CMOS process. The results show the transconductance tuning ratio of 23 and the IM3 performance of -68.5 dB.
Linear low voltage nano-scale CMOS transconductor
(2011-01-01)
Lo, Tien-Yu
;
Hung, Chung-Chih
;
Lo, Chi-Hsiang
;
電機工程學系
;
Department of Electrical and Computer Engineering
This paper presents a high linearity MOSFET-only transconductor based on differential structures. While a precise BSIM4 transistor model is introduced through analysis, the linearity can be improved by mobility compensation techniques as the device size is scaled down in the nano-scale CMOS technology. When the compensation utilizes transistors in subthreshold region, rather than the transistors in saturation region, the value of transconductance can be maintained. The circuit is fabricated in TSMC 0.18-mu m CMOS process. The measurement results show 18 dB improvement of the proposed version, and 65 dB HD3 can be achieved for a 2.1 MHz 700 mV(pp) differential input. The static power consumption under 1-V power supply voltage is 183 mu W. Measurement results demonstrate the agreement with theoretical analyses.