Browsing by Author "Lo, Chi-Wei"

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ERROR-RESILIENT SEQUENTIAL CELLS WITH SUCCESSIVE TIME BORROWING FOR STOCHASTIC COMPUTING
(2016)
Liu, Wei-Chang
;
Chan, Ching-Da
;
Huang, Shuo-An
;
Lo, Chi-Wei
;
Yang, Chia-Hsiang
This paper presents error-resilient sequential building blocks with time-borrowing capability without extra latches and generated clocks. The circuits are able to recover the timing errors caused by PVT variations and/or over-voltage scaling by up to half a cycle. Unlike prior works, the timing errors can be recovered dynamically through successive time borrowing without stalled cycles, retaining a constant throughput. The circuit structure can be applied to both ASICs and microprocessors. The proposed sequential cells are highly compatible with current cell-based IC design flow, for both feed-forward and feedback datapaths. As a proof of concept, a design with key DSP building blocks has been verified. The results show that the performance of the DSP modules is improved by 13-15% in the worst-case operation condition, yielding a promising solution for stochastic computing under an unreliable operation condition.