Browsing by Author "Lo, Chun-Li"

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3D Vertical TaOx/TiO2 RRAM with over 10(3) Self-Rectifying Ratio and Sub-mu A Operating Current
(2013-01-01)
Hsu, Chung-Wei
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Wan, Chia-Chen
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Wang, I-Ting
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Chen, Mei-Chin
;
Lo, Chun-Li
The 3D double-layer vertical RRAM with ultralow sub-mu A operating current and high self-rectifying ratio over 10(3) has been demonstrated for the first time. This Ta/TaOx/TiO2/Ti interfacial switching device overcomes the intrinsic trade-off between operating current and variability in filamentary RRAMs and shows promising potential for high-density data storage.
Bipolar Ni/TiO2/HfO2/Ni RRAM With Multilevel States and Self-Rectifying Characteristics
(2013-07-01)
Hsu, Chung-Wei
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Hou, Tuo-Hung
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Chen, Mei-Chin
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Wang, I-Ting
;
Lo, Chun-Li
To be compatible with 3-D vertical crossbar arrays, a TiO2/HfO2 bilayer resistive-switching memory (RRAM) cell sandwiched between Ni electrodes is developed. The proposed device has numerous highly desired features for the implementation of 3-D vertical RRAM, including: 1) stable bipolar resistive switching; 2) forming free; 3) self-compliance; 4) self-rectification; 5) multiple resistance states; and 6) room-temperature process. The resistive switching and current rectification are attributed to oxygen vacancy migration in HfO2 and potential barrier modulation of the asymmetric TiO2/HfO2 tunnel barrier. The rectification ratio up to 10(3) is capable of realizing a single-crossbar array up to 16 Mb for future high-density storage class memory applications.
Dependence of Read Margin on Pull-Up Schemes in High-Density One Selector-One Resistor Crossbar Array
(2013-01-01)
Lo, Chun-Li
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Hou, Tuo-Hung
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Chen, Mei-Chin
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Huang, Jiun-Jia
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電子工程學系及電子研究所
This paper reports on comprehensive analytical and numerical circuit analyses on the read margin of the one selector-one resistor (1S1R) resistive-switching crossbar array. These analyses are based on the experimental characteristics of the 1S1R cells and provide a valuable insight into their potential for ultrahigh-density data storage. Three read schemes, namely, one bit-line pull-up (One-BLPU), all bit-line pull-up (All-BLPU), and partial bit-line pull-up (Partial-BLPU), are investigated. In contrast to the One-BLPU scheme, the All-BLPU scheme can realize a large crossbar array of 16 Mb, even when the line resistance is nonneg-ligible because the effective resistance at the sneak current path is substantially less sensitive to the array size. Additionally, the Partial-BLPU scheme can be used to reduce power consumption if random read access is desirable. Finally, the effects of line resistance on the read and write margins are discussed.
On the Potential of CRS, 1D1R, and 1S1R Crossbar RRAM for Storage-Class Memory
(2013)
Lo, Chun-Li
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Chen, Mei-Chin
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Huang, Jiun-Jia
;
Hou, Tuo-Hung
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電子物理學系
Statistical Model and Rapid Prediction of RRAM SET Speed-Disturb Dilemma
(2013-11-01)
Luo, Wun-Cheng
;
Liu, Jen-Chieh
;
Lin, Yen-Chuan
;
Lo, Chun-Li
;
Huang, Jiun-Jia
A comprehensive study of SET speed-disturb dilemma in resistive-switching random access memory (RRAM) is presented using statistically based prediction methodologies, accounting for the stochastic nature of SET. An analytical percolation model has been successful in explaining the statistical Weibull distribution of SET time and SET voltage in addition to the power-law voltage-time dependence. Two prediction methodologies using constant voltage stress (CVS) and ramp voltage stress (RVS) are proposed to evaluate the SET speed-disturb properties. The RVS method reduces analysis time and cost and yields equivalent results as the CVS method. Furthermore, the RVS method is used to evaluate the device design space and the current status of RRAM technology to meet the strict requirement of the SET speed-disturb dilemma.