Browsing by Author "Lo, KY"

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Characterization and reliability of low dielectric constant fluorosilicate glass and silicon rich oxide process for deep sub-micron device application
(2001-11-01)
Cheng, YL
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Wang, YL
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Liu, CW
;
Wu, YL
;
Lo, KY
Fluorosilicate Glass (FSG) with low dielectric constant currently has been replaced as an alternative to SiO2 for device speed improvement. However, several integration aspects, such as Fluorine (F) distribution, F thermal stability, gap fill capability, capacitance reduction and via resistance of FSG prepared by the high density plasma (HDP) chemical vapor deposition (CVD) method are of concern for sub-0.18-mum devices. In this study, HDP-FSG films show different F concentrations at different locations on an 8-inch wafer. In addition, the FSG film shows poor thermal stability and F diffuses out of the film after high temperature annealing and the pressure cook test (PCT). However, the thermal stability of FSG film can be improved by capping with an oxide layer. The results indicate that silicon rich oxide (SRO) has a better effect at blocking the F diffusion out of FSG films at high temperature than plasma enhanced oxide (PE-OX). For the gap fill capability, HDP-FSG can fill all 0.23-mum gaps and some of the 0.21-mum gaps with an aspect ratio <3.8 but not the 0.19-mum gaps. A 8000 Angstrom HDP-FSG film with 600 Angstrom USG liner and 2000 Angstrom cap layer shows approximately 7.5 to 7.7% capacitance reduction on 0.23/0.23-mum gaps when compared with USG (undoped silicate glass). In addition, FSG has a larger capacitance reduction on the wider metal lines than the thinner metal lines at the same gap size due to a capacitance fringe effect. The via resistance for 0.26 mum unlanded via (which allow minor photo mis-alignment) of HDP-FSG film is also similar to that of USG. (C) 2001 Elsevier Science B.V. All rights reserved.
Copper surface protection with a completely enclosed copper structure for a damascene process
(2004-01-30)
Wang, TC
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Hsieh, TE
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Wang, YL
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Wu, YL
;
Lo, KY
As integrated circuit manufacture moving to copper interconnection for the most advanced products, protection of copper (Cu) surfaces becomes a major challenge for the back-end-of-line manufacturing process. The damages on Cu, such as Cu corrosion and oxidation, are often observed on wafers when exposing bare Cu surface in the presence of moisture and/or acidic gases. Furthermore, the Cu oxide results in poor adhesion both at Cu/barrier layer and Cu/stop layer interfaces. In this work, a novel Cu dual damascene structure which completely encloses the Cu surface with a tantalum nitride layer is presented. This capping layer avoids the Cu corrosion and oxidation due to its ability to keep moisture and acid off and away from the Cu surface. (C) 2003 Elsevier Science B.V. All rights reserved.
Effect of deposition temperature, on thermal stability in high-density plasma chemical vapor deposition fluorine-doped silicon dioxide
(2004-05-01)
Cheng, YL
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Wang, YL
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Chen, HW
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Lan, JL
;
Liu, CP
Thermal stability of fluorine-doped silicon dioxide films deposited by high-density plasma chemical vapor deposition as a function of deposition temperature were investigated in this study. Both thermal desorption spectrum and annealing test results show that SiOF films deposited above 400 degreesC have better thermal stability. Furnace annealing data indicate that non -Si-F- bonding fluorine does exist in low-deposition-temperature SiOF films. Furthermore, secondary-ion mass spectrometer results also reveal that the fluorine in SiOF films with a lower-deposition temperature is easily diffused out and turned into the underlayer, which results in less thermally stable SiOF films. Moreover, short-loop simulation results have been subsequently tested and it was concluded that the deposition temperature of the SiOF film is extremely important for thermal stability. (C) 2004 American Vacuum Society.
Evaluation of advanced chemical mechanical planarization techniques for copper damascene interconnect
(2004-01-30)
Chen, KW
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Wang, YL
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Liu, CP
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Yang, K
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Chang, L
According to rapid development of CMP technology, the difference of polishing methods would be applied for copper damascene interconnect. These methods include conventional rotary, linear, oscillation platform. The advantages of these platform would highlighted in uniformity control, stability of removal rate, planarization efficiency, throughput promotion, lower cost of ownership, even dishing and erosion effect integrated with slurry. This paper presented our experience to compare the uniformity, removal rate and planarization efficiency of Cu-CMP between various polishing platforms. In convection, the rotary or oscillation platform would be usually applied in oxide and tungsten CMP, due to the robust air-back carrier and rigid platen to polish the wafer, which performs the good reliability on wafer-to-wafer thickness and endpoint detection. However, the linear polisher is made of the air-bearing moving belt and self-rotated carrier and would provide the wider uniformity and planarization control window than others. In addition,, the simulation model would explain the difference from mechanic design and wafer moving paths between various polishing techniques. Hence, the trade-off advantage and application between various platforms would be compensated and integrated with slurry, conditioners and coming thickness profile from copper plating. It can achieve the optimization of Cu-CMP process. (C) 2003 Elsevier B.V. All rights reserved.
Integration of a stack of two fluorine doped silicon oxide film with ULSI interconnect metallization
(2004-01-15)
Cheng, YL
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Wang, YL
;
Liu, CP
;
Wu, YL
;
Lo, KY
Recently, fluorosilicate glass (FSG) has received much attention for application in microelectronics manufacturing due to its low dielectric constant and stable gap-filling ability. Although FSG films have been demonstrated as potential inter metal dielectrics (IMD) for sub-micron devices, integrating a stack of two fluorine doped silicon oxide film deposited on a high-density plasma chemical vapor deposition (HDP-CVD) system for gap filling and a plasma-enhanced chemical vapor deposition (PECVD) system for throughput has not been fully investigated. In this research, an excellent and exceptionally stable process was demonstrated for a stack of HDP-CVD FSG and PECVD FSG layers. Cracks that result from multi-level metal technology were eliminated when higher compressive stress PECVD FSG film was implemented as a capping layer. An 11% capacitance reduction was achieved when comparing a stack of FSG films to undoped silicon oxide. No problem occurred for photo, via etching and chemical mechanical polishing of FSG film. The FSG layer stack's via resistance (Rc(-)Via) as well as a full HDP-FSG scheme is comparable. These results are very promising for the integration of FSG films as inter metal dielectric for devices. (C) 2003 Elsevier B.V. All rights reserved.
Integration of MOCVD titanium nitride with collimated titanium and ion metal plasma titanium for 0.18-mu m logic process
(2001-11-01)
Lan, JK
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Wang, YL
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Lo, KY
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Liu, CP
;
Liu, CW
Both collimated titanium (CO-Ti) and ion metal plasma titanium (IMP-Ti) have been widely used for plug liner layers. The focused ion beam (FIB) images of these films show that the IMP-Ti surface is granular and the CO-Ti surface is amorphous. It is concluded that the lower reflectivity and resistivity of IMP-Ti films are caused by the fact that IMP-Ti has a larger grain than that of the CO-Ti films. We define a grain size factor (GF) and find that the activation energy of grain growth of IMP-Ti film is 3.8 times larger than that of CO-Ti film. The electric measurement of vias resistance shows that IMP-Ti plug liner gives 13.6% higher via resistance and broader distribution than that of the CO-Ti plug liner. From the experimental data, we can conclude that there are three factors that make the IMP Ti plug liner process have higher vias resistance. These three factors are IMP-Ti resistivity, IMP-Ti thickness and CVD TiN thickness. (C) 2001 Elsevier Science B.V. All rights reserved.
Novel strategies of FSG-CMP for within-wafer uniformity improvement and wafer edge yield enhancement beyond 0.18 micro technologies
(2001)
Chen, KW
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Wang, YL
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Chang, L
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Liu, CW
;
Lin, YK
The low-K films and higher multiple stacked layers would be widely applied for ultra large-scale integrated circuits [1][2]. However for 8" (200mm) or 12" (300mm) wafer the phenomena of wafer edge collapsing in higher interlayer low-K dielectric film causes from CMP polishing effect. (Shown in Fig. 1). Conventionally a amount of work has been developed in the optimization of different parameters, such as low pressure and high speed [3], metal dummy filling [4], harder pad used [4], and design of polishing head in order to resolve the problems. But these methods only engaged in design of experiment, not addressed in CMP theory of edge collapsing and controlling way. In this paper we will discuss the theory applied in Preston equation to explain the polishing behavior in wafer edge. In advance, to implement the theory, we adopted novel strategies, including of different polishing head (sweep) vibration and pad edge sprayer methods, even new wafer retaining ring design and novel delivery slurry methods in advance. The characteristics of within wafer nonuniformity and edge profile against CMP polishing low-k films, fluorinated silicate glass (FSG), would be evaluated in this new strategy action. Besides, the dimension of metal line and VIA, and edge die-yield can be directly responded to the edge profile improvement. From the action results, the average 7 similar to 10% yield improvement of 0.18 technology can be achieved, especially 15% edge-die yield improvement. The edge profile could promote the phenomena of no collapsing from the original 75 mm to 95 mm of wafer center-to-edge distance, excluding 3 mm edge of 8-inch wafer. These high efficient strategies for within-wafer planarization and edge profile is also proven and fulfilled with the reducing over 50% VIA CD deviation on the rule of lithography.
Optimization of post-N-2 treatment and undoped-Si-glass cap to improve metal wring delamination in deep submicron high-density plasma-fluorinated silica glass intermetal dielectric application
(2004-07-01)
Cheng, YL
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Wang, YL
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Lan, JK
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Wu, SA
;
Chang, SC
Integration issues of metal line delamination from fluorinated silica glass (FSG) in deep submicron intermetal dielectric applications were investigated in this study. A metal line peeled off after a nonoptimized in situ deposition of undoped-silicon-glass (USG; SiO2) capping layer followed the post-FSG-chemical mechanical polishing N-2 treatment. It was found that higher bias power and longer process time of N-2 treatment led to more active fluorine species diffusing from the FSG films to the USG surface, which might react with subsequent Ti/TiN/W metal layer and result in metal delamination. Using plasma-enhanced N-2 treatment and ex situ USG capping with lower initial deposition temperature by extra cooling step, the stability of the FSG films was improved and resulted in a robust structure without metal peeling. (C) 2004 American Vacuum Society.