Browsing by Author "Lo, Kai-Yu"

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A Low-Power Level-Converting Double-Edge-Triggered Flip-Flop Design
(2013-10-01)
Wang, Li-Rong
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Lo, Kai-Yu
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Jou, Shyh-Jye
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
This paper proposes a new double-edge-triggered implicitly level-converting flip-flop, suitable for a low-power and low-voltage design. The design employs a sense amplifier architecture to reduce the delay and power consumption. Experimentally, when implemented with a 130-nm, single-V-t and 0.84 V V-DD process, it achieves 64% power-delay product (PDP) improvement, and moreover, 78% PDP improvement when implemented with a mixed-V-t technology, as compared to that of the classic double-edge-triggered flip-flop design.
A Varactor-Based All-Digital Multi-Phase PLL with Random-Sampling Spur Suppression Techniques
(2016-04-01)
Chang, Chia-Wen
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Lo, Kai-Yu
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Ibrahim, Hossameldin A.
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Su, Ming-Chiuan
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Chu, Yuan-Hua
This paper presents a varactor-based all-digital phase-locked loop (ADPLL) with a multi-phase digitally controlled oscillator (DCO) for near-threshold voltage operation. In addition, a new all-digital reference spur suppression (RSS) circuit with multiple phases random-sampling techniques to effectively spread the reference clock frequency is proposed to randomize the synchronized DCO register behavior and reduce the reference spur. Because the equivalent reference clock frequency is reserved, the loop behavior is maintained. The area of the proposed spur suppression circuit is only 4.9% of the ADPLL (0.038 mm(2)). To work reliably at the near-threshold region, a multi-phase DCO with NMOS varactors is presented to acquire precise frequency resolution and high linearity. In the near-threshold region (V-DD = 0.52 V), the ADPLL only dissipates 269.9 mu W at 100 MHz output frequency. It has a reference spur of -52.2 dBc at 100 MHz output clock frequency when the spur suppression circuit is deactivated. When the spur suppression circuit is activated, the ADPLL shows a reference spur of 57.3 dBc with the period jitter of 0.217% UI.