Browsing by Author "Lo, Tien-Yu"

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1-V linear CMOS transconductor with-65 dB THD in nano-scale CMOS technology
(2007)
Lo, Tien-Yu
;
Hung, Chung-Chih
;
電信工程研究所
;
Institute of Communications Engineering
This paper presents a high linearity MOSFET-only transconductor based on differential structures. The linearity is improved by mobility compensation techniques as the device size is scaled down in the nano-scale CMOS technology. Transconductance tuning could be achieved by transistors operating in the linear region. The simulated total harmonic distortion (THD) under 1-V power supply voltage shows 12 dB improvement of the proposed version, and -65 dB TTID can be achieved for a 1 MHz 700 mV(pp) differential input. Monte-Carlo simulation over the corner variation and transistor mismatch guarantees the shown performance. The static power consumption is 130 mu W. Simulation results demonstrate the agreement with theoretical analyses.
A 1 GHz Equiripple Low-Pass Filter With a High-Speed Automatic Tuning Scheme
(2011-02-01)
Lo, Tien-Yu
;
Hung, Chung-Chih
;
電機工程學系
;
Department of Electrical and Computer Engineering
A continuous-time fourth-order equiripple linear phase G(m) - C filter with an automatic tuning circuit is presented. A high speed OTA based on the inverter structure is realized. The combined common-mode feedforward and common-mode feedback circuit ensures the input and output common-mode stability. The gain performance could be maintained by combining an equivalent negative resistor circuit at the output nodes. Transconductance tuning can be achieved by adjusting the bulk voltage by using the deep-NWELL technology. The modified automatic tuning circuit relaxes the speed requirement of the tuning blocks. Through the use of the operational transconductance amplifier as a building block with the automatic tuning scheme, the filter -3 dB cutoff frequency is 1 GHz with the group delay less than 4% variation up to 1.5 fc frequency. The -43 dB of IM3 at filter cutoff frequency is obtained with -4 dbm two-tone signals. Implemented in 0.18-mu m CMOS process, the chip occupies 1 mm(2) and consumes 175 mW at a 1.5-V supply voltage.
A 1 GHz OTA-Based low-pass filter with a high-speed automatic tuning scheme
(2007)
Lo, Tien-Yu
;
Hung, Chung-Chih
;
電信工程研究所
;
Institute of Communications Engineering
A continuous-time 4th-order equiripple linear phase G.-C filter with an automatic tuning circuit is presented. A high speed OTA based on the inverter structure is realized. The combined CMFF and CMFB circuit ensures the input and output common-mode stability. The gain performance could be maintained by combining a negative resistor at the output nodes. Transconductance tuning can be achieved by adjusting the bulk voltage by using the Deep-NWELL technology. Through the use of the OTA as a building block with a modified automatic tuning scheme, the filter -3dB cutoff frequency is 1GHz with the group delay less than 4% variation up to 1.5fc frequency. The -43dB of IM3 at filter cutoff frequency is obtained with -4dbm two tone signals. Implemented in 0.18-mu m CMOS process, the chip occupies 1mm(2) and consumes 175mW at a 1.5-V supply voltage.
A 1-V 50-MHz pseudodifferential OTA with compensation of the mobility reduction
(2007-12-01)
Lo, Tien-Yu
;
Hung, Chung-Chih
;
電信工程研究所
;
Institute of Communications Engineering
This brief presents a high-linearity operational transconductance amplifier (OTA) based on pseudodifferential structures. The linearity is improved by mobility compensation techniques as the device size is scaled down to achieve high speed operation. Transconductance tuning could be achieved by a MOS operating in the linear region. The OTA fabricated in the 0.18-mu m CMOS process occupies a small area of 4.5 X 10(-3) mm(2). The measured third-order intermodulation (IM3) distortion with a 400 mV(pp) differential input under 1-V power supply voltage remains below -52 dB for frequency up to 50 MHz. The static power consumption is 2.5 mW. Experimental results demonstrate the agreement with theoretical analyses.
A 1-V G(m)-C Low-Pass Filter for UWB Wireless Application
(2008)
Lo, Tien-Yu
;
Hung, Chung-Chih
;
電信工程研究所
;
Institute of Communications Engineering
This paper proposes a high performance G.-C equiripple linear phase low-pass filter for UWB wireless application. The proposed OTA is designed under low power supply voltage consideration while its gain, excess phase, and linearity are well maintained. The common-mode control system, including common-mode feedback (CMFB) and common-mode feedforward (CMFF) circuits, is added to ensure stability of the proposed filter. Measurement results show that the inter-modulation distortion (IM3) of -40dB can be achieved with 250MHz 400mV(pp) balanced differential input signals. The filter works in 1-V supply voltage and its power consumption is 32mW.
A 250 MHz low voltage low-pass G(m)-C filter
(2012-06-01)
Lo, Tien-Yu
;
Hung, Chung-Chih
;
電機工程學系
;
Department of Electrical and Computer Engineering
A high speed and high linearity G(m)-C low-pass filter is presented. The proposed OTA is designed under low power supply voltage consideration while its gain, excess phase, and linearity are well maintained. The common-mode control system, including common-mode feedback and common-mode feedforward circuits, is added to ensure stability of the proposed filter. Measurement results show that the inter-modulation distortion of -40 dB can be achieved with 250 MHz 400 mV(pp) differential input signals. The filter works in 1 - V supply voltage and its power consumption is 32 mW.
A 40-MHz double differential-pair CMOS OTA with-60-dB IM3
(2008-02-01)
Lo, Tien-Yu
;
Hung, Chung-Chih
;
電信工程研究所
;
Institute of Communications Engineering
A configuration of a linearized operational transconductance amplifier (OTA) for low-voltage and high-frequency applications is proposed. By using double pseudodifferential pairs and the source-degeneration structure under nano-scale CMOS technology, the norlinearity caused by short channel effect from a small feature size can be minimized. A robust common-mode control system is designed for input and output common-mode stability and thus reduces distortion caused by common-mode voltage variation. Mining ability can be achieved by using MOS transistors in the linear region. The linearity of the OTA is about -60-dB third-order inter-modulation (IM3) distortion for up to 0.9 V-pp at 40 MHz. This OTA was fabricated by the TSMC 180-nm deep n-well CMOS process. It occupies a small area of 15.1 X 10(-3) mm(2) and the power consumption is 9.5 mW under a 1.5-V supply voltage.
A G(m)-C continuous-time analog filter for IEEE 802.11 a/b/g/n wireless LANs
(2007)
Lo, Tien-Yu
;
Kao, Cheng-Sheng
;
Hung, Chung-Chih
;
電信工程研究所
;
Institute of Communications Engineering
A CMOS transconductor for multi-mode wireless channel selection filter is presented. The linear transconductor is designed based on the flipped-voltage follower (FVF) circuit and an active resistor to achieve the transconductance tuning. The transconductance tuning can be obtained by changing the bias current of the active resistor. A third-order Butterworth low-pass filter implemented with the transconductors was designed by TSMC 0.18-mu m CMOS process. The results show that the filter can operate with the cutoff frequency of 10 MHz to 20 MHz. The tuning range would be suitable for the specifications of IEEE 802.11a/b/g/n Wireless LANs under the consideration of saving chip areas. In the design, the maximum power consumption is 13 mW with the cutoff frequency of 20 MHz under a 1.8-V supply voltage.
A high speed and high linearity OTA in 1-V power supply voltage
(2006)
Lo, Tien-Yu
;
Hung, Chung-Chih
;
電信工程研究所
;
Institute of Communications Engineering
This paper proposes a high performance operational transconductance amplifier (OTA) which is based on the pseudo-differential architecture with addition of linearity improved circuits. The OTA is designed under low power supply voltage consideration while its gain, excess phase, and linearity are well maintained. A common-mode control system, including common-mode feedback (CMFB) and common-mode feedforward (CMFF) circuits, is added to ensure stability at high frequency. Results show that the topology can achieve the total harmonic distortion (THD) to the -56dB with 100MHz balanced differential input signals up to 300mVpp at 1-V supply voltage by the TSMC 0.18 mu m CMOS process. Its power consumption is 1.8mW.
A low-power CMOS voltage reference circuit based on subthreshold operation
(2007)
Chang, Chia-Wei
;
Lo, Tien-Yu
;
Chen, Chia-Min
;
Wu, Kuo-Hsi
;
Hung, Chung-Chih
A low power CMOS Voltage Reference Circuit was designed and implemented by TSMC 0.18-mu m CMOS process. The voltage reference circuit uses the V-GS difference between two MOSFETs operating in the weak-inversion region to generate the voltage with positive temperature coefficient The reference voltage can be obtained by combining the weighted V-GS difference with weak-inversion V-GS voltage, which has a negative temperature coefficient. This circuit provides a nominal reference voltage of 621 mV, a temperature coefficient of 11.5 ppm/degrees C in [-20 degrees C-120 degrees C] from a 1.5 V supply voltage. The line regulation of the reference voltage is 6 mV/V when the supply voltage is increased from 1.5 V to 3 V. The chip area is 0.132 mm(2) and dissipates 17.25 mu W at room temperature. By connecting a 0.22 mu F loading capacitor, the measured noise density at 100 Hz and 100 kHz is 0.14 mu V/root Hz and 22.2 mu V/root Hz, respectively.
A wide tuning range G(m)-C continuous-time analog filter
(2007-04-01)
Lo, Tien-Yu
;
Hung, Chung-Chih
;
電信工程研究所
;
Institute of Communications Engineering
A CMOS operational transconductance amplifier (OTA) for low-power and wide tuning range filter application is proposed in this paper. The OTA can work from the weak inversion region to the strong inversion region to maximize the transconductance tuning range. The transconductance can be tuned by changing its bias current. A fifth-order Elliptic low-pass filter implemented with the OTAs was integrated by TSMC 0.18-mu m CMOS process. The filter can operate with the cutoff frequency of 250 Hz to 1 MHz. The wide tuning range filter would be suitable for multi-mode applications, especially under the consideration of saving chip areas. The third-order inter-modulation (IM3) of -40 dB was measured over the tuning range with two tone input signals. The power consumption is 0.8 mW at 1-MHz cutoff frequency and 1.8-V supply voltage with the active area less than 0.3 mm(2).
A Wide Tuning Range G(m)-C Filter for Multi-Mode CMOS Direct-Conversion Wireless Receivers
(2009-09-01)
Lo, Tien-Yu
;
Hung, Chung-Chih
;
Ismail, Mohammed
;
電信工程研究所
;
Institute of Communications Engineering
A third-order channel selection filter for multi-mode direct-conversion receivers is presented. The filter is designed with a Butterworth prototype and with the target wireless applications of Bluetooth, cdma2000, Wideband CDMA, and IEEE 802.11a/b/g/n wireless LANs. Linear-region MOS transistors are used to perform voltage-to-current conversion. The wide tuning range is achieved by the current multipliers and linear voltage-to-current converters. Implemented in the TSMC 0.18 mu m CMOS process, the measurement results show that the filter can operate successfully over a cutoff frequency range of 500 kHz to 20 MHz, and is compliant with the requirements of different wireless applications. The power consumption is 4.1 mW to 11.1 mW for minimum and maximum cutoff frequencies respectively from a 1.2 V supply voltage. The circuit performance compares favorably with previously reported works.
A wide tuning range G(m)-C filter for multi-mode direct-conversion wireless receivers
(2007)
Lo, Tien-Yu
;
Hung, Chung-Chih
;
Ismail, Mohammed
;
電信工程研究所
;
Institute of Communications Engineering
A third-order channel selection filter for multi-mode direct-conversion receiver is presented. The filter is designed based on the Butterworth prototype with the target applications of Bluetooth, cdma2000, Wideband CDMA, and IEEE 802.11 a/b/g/n wireless LANs. Linear region MOS transistors are used to perform the voltage-to-current conversion. The wide tuning range can be achieved by the translinear loop followed by the linear voltage-to-current converter. Implemented in the TSMC 0.18-mu m CMOS process, the measurement results show that the filter can operate with the cutoff frequency of 500 kHz to 20 MHz, and thus meet the requirement of different wireless applications. In the design, the maximum power consumption is 11.1 mW under a 1.2-V supply voltage. The figure of merit (FOM) is favorably compared with the other previously reported works.
A-68.5 dB IM3 Low-Voltage CMOS Transconductor with Wide Tuning Range
(2010-08-01)
Lo, Tien-Yu
;
Hung, Chung-Chih
;
Lo, Chi-Hsiang
;
電機工程學系
;
Department of Electrical and Computer Engineering
A CMOS transconductor for multi-mode application is presented. The transconductor includes a voltage-to-current converter and a current multiplier. Voltage-to-current conversion employs linear region MOS transistors, and the conversion features high linearity over a wide input swing range. The current multiplier, which operates in the weak inversion region, provides a wide transconductance tuning range without degrading the linearity. The transconductor was designed and fabricated in the TSMC 0.18-mu m CMOS process. The results show the transconductance tuning ratio of 23 and the IM3 performance of -68.5 dB.
An active device based wide tuning range CMOS transconductor
(2012-04-01)
Lo, Tien-Yu
;
Hung, Chung-Chih
;
電子物理學系
;
Department of Electrophysics
A CMOS transconductor for wide tuning range filter application is presented. The linear transconductor is designed based on the flipped-voltage follower (FVF) circuit and can work in the weak, moderate, and strong inversion regions to maximize the transconductance tuning range. The transconductance tuning can be achieved by changing the bias current of the active resistor, and a ratio of 28 is obtained. The transconductor was evaluated by using TSMC 0.18 mu m CMOS process, and the total harmonic distortion (THD) of -56 dB can be obtained by giving a 12 MHz 0.4 Vpp input swing signal. In the design, the maximum power consumption is 2 mW with the transconductance of 1.1 mS under a 1.8 V supply voltage.
CMOS voltage reference based on threshold voltage and thermal voltage
(2010-01-01)
Lo, Tien-Yu
;
Hung, Chung-Chih
;
Ismail, Mohammed
;
電信工程研究所
;
Institute of Communications Engineering
Linear low voltage nano-scale CMOS transconductor
(2011-01-01)
Lo, Tien-Yu
;
Hung, Chung-Chih
;
Lo, Chi-Hsiang
;
電機工程學系
;
Department of Electrical and Computer Engineering
This paper presents a high linearity MOSFET-only transconductor based on differential structures. While a precise BSIM4 transistor model is introduced through analysis, the linearity can be improved by mobility compensation techniques as the device size is scaled down in the nano-scale CMOS technology. When the compensation utilizes transistors in subthreshold region, rather than the transistors in saturation region, the value of transconductance can be maintained. The circuit is fabricated in TSMC 0.18-mu m CMOS process. The measurement results show 18 dB improvement of the proposed version, and 65 dB HD3 can be achieved for a 2.1 MHz 700 mV(pp) differential input. The static power consumption under 1-V power supply voltage is 183 mu W. Measurement results demonstrate the agreement with theoretical analyses.
Low-voltage multi-mode Gm-C channel selection filter for mobile applications
(2007)
Lo, Tien-Yu
;
Hung, Chung-Chih
;
電信工程研究所
;
Institute of Communications Engineering
A CMOS transconductor for multi-mode mobile channel selection filter is presented. The transconductor includes a voltage-to-current converter and a current multiplier. Voltage-to-current conversion employs linear region MOS transistors and the circuit features high linearity over a wide input swing range. The current multiplier which operates in the weak inversion region provides a wide transconductance tuning range without degrading the linearity. A third-order Butterworth low-pass filter implemented with the transconductors was designed by TSMC 0.18-mu m CMOS process. The measurement results show that the filter can operate with the cutoff frequency of 135 kHz to 2.2 MHz. The tuning range and the linearity performance would be suitable for the wireless specifications of GSM, Bluetooth cdma2000, and Wideband CDMA. In the design, the maximum power consumption at the highest cutoff frequency is 2 mW under a 1-V supply voltage.
Multimode G(m)-C channel selection filter for mobile applications in 1-V supply voltage
(2008-04-01)
Lo, Tien-Yu
;
Hung, Chung-Chih
;
電信工程研究所
;
Institute of Communications Engineering
A CMOS transconductor for multimode channel selection filter is presented. The transconductor includes a voltage-to-current converter and a current multiplier. Voltage-to-current conversion employs linear region MOS transistors, and the conversion features high linearity over a wide input swing range. The current multiplier which operates in the weak inversion region provides a wide transconductance tuning range without degrading the linearity. A third-order Butter-worth low-pass filter implemented. with the transconductors was designed by TSMC 0.18-mu m CMOS process. The measurement results show that the filter can operate with the cutoff frequency of 135 kHz to 2.2 MHz. The tuning range and the linearity performance would be suitable for the wireless specifications of GSM, Bluetooth, cdma2000, and wide-band CDMA. In the design, the maximum power consumption at the highest cutoff frequency is 2 mW under a 1-V supply voltage.
Negative current feedback OTA with application to 250 MHz Gm-C filter
(2012-10-01)
Lo, Tien-Yu
;
Kuo, Chih-Lung
;
Hung, Chung-Chih
;
電機工程學系
;
Department of Electrical and Computer Engineering
A 4th-order low-pass Gm-C filter for high speed wireless/wireline system is realized in 0.18 mu m CMOS process. The high speed filter is designed based on operational transconductance amplifier (OTA) biquad sections. As well known, large transconductance is required for high speed applications, and thus the conventional source degeneration topology, which operates with the trade-off between linearity and transconductance, should be improved. In this paper, the proposed OTA uses negative current feedback topology to maintain linearity while increasing transconductance for high speed application, and a 4th-order low-pass filter is realized by using the OTA as a building block. Fabricated in 0.18 mu m CMOS technology, the -3 dB filter frequency response at 250 MHz is obtained. The measured HD3 performance is about -40 dB while the filter consumes 32 mW power at a 1.8 V supply voltage.