Browsing by Author "Lo, WY"

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A method for calibrating a motorized object rig
(2006)
Huang, PH
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Tsai, YP
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Lo, WY
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Shih, SW
;
Chen, CS
Object Movies (OMs) have been successfully used in many applications. However, the techniques for acquiring OMs still need to be improved if high-quality and efficient OMs are desired. In this paper, we present a method for calibrating a motorized object rig to facilitate the acquisition of OMs. We first apply the CPC kinematic model to formulate the 3D configuration of the device, and then propose a method to estimate the parameters of the CPC model of the device. Furthermore, a visual tool is provided for users to adjust the controllable axes of the rig according to the estimated results. After this calibration, more accurate camera parameters can be obtained and then be used for different purposes. In this work, we use the parameters to reconstruct, from an OM, the 3D model of the object, and then adjust the OM according to the center of the 3D model so that a high-quality OM can be obtained for rendering.
Abnormal ESD failure mechanism in high-pin-count BGA packaged ICs due to stressing nonconnected balls
(2004-03-01)
Lo, WY
;
Ker, MD
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電機學院
;
College of Electrical and Computer Engineering
An abnormal failure mechanism due to ESD pulse applied on the nonconnected (NC) solder balls of a high-pin-count (683 balls) BGA packaged chipset IC is presented. The ESD test results of the IC product were found below human-body-model (HBM) 2 kV when stressing all balls or only stressing NC balls, but above HBM 3 kV when stressing all balls excluding NC balls. Failure analyses, including scanning electron microscopy (SEM) photographs and the measurement of current waveforms during ESD discharging event, have been performed. With a new proposed equivalent model, a clear explanation on this unusual phenomenon is found to have a high correlation to the small capacitor method (SCM). Several solutions to overcome this failure mechanism are also discussed.
Analysis and prevention on NC-ball induced ESD damages in a 683-pin BGA packaged chipset IC
(2003-09-01)
Lo, WY
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Ker, MD
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電機學院
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College of Electrical and Computer Engineering
An abnormal failure mechanism due to ESD zapping on the Non-Connected (NC) balls of a 683-pin BGA packaged chipset IC is presented. Failure analyses, including Scanning Electronic Microscopy (SEM) photographs and the measurement of current waveforms during ESD zapping, had been performed with a new proposed equivalent circuit to give clear explanation on this unusual phenomenon. Several methods to prevent such failure mechanism are also discussed. (C) 2003 Elsevier Ltd. All rights reserved.
Compact layout rule extraction for latchup prevention in a 0.25-mu m shallow-trench-isolation silicided bulk CMOS process
(2001)
Ker, MD
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Lo, WY
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Chen, TY
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Tang, H
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Chen, SS
An experimental extraction to find the area-efficient compact layout rules to prevent latchup in bulk CMOS IC's is proposed. The layout rules are extracted from the test patterns with different layout spacings or distances. A new efficient latchup prevention design, by adding the additional internal guard rings between the I/O cells and the internal core circuits, has been successfully proven in a 0.25-mum shallow-trench-isolation (STI) silicided bulk CMOS process. Through detailed experimental verification including temperature effect, the proposed extraction method to define compact layout rules has been established to save the silicon area of CMOS IC's, but still to maintain high enough latchup immunity in bulk CMOS IC's.
Design on the low-leakage diode string for using in the power-rail ESD clamp circuits in a 0.35-mu m silicide CMOS process
(2000-04-01)
Ker, MD
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Lo, WY
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
A new design on the diode string with very tow leakage current is proposed for using in the ESD clamp circuits across the power rails. By adding an NMOS-controlled lateral SCR (NCLSCR) device into the stacked diode string, the Leakage current of this new diode string with six stacked diodes at 5-V (3.3-V) forward bias can be reduced to only 2.1 (1.07) nA at a temperature of 125 degrees C in a 0.35-mu m silicide CMOS process, whereas the previous designs have a leakage current in the order of mA, The total blocking voltage of this new design with NCLSCR can be linearly adjusted by changing the number of the stacked diodes in the diode string without causing latch-up danger across the power rails. From the experimental results, the human-body-model ESD level of the ESD clamp circuit with the proposed low-leakage diode string is greater than 8 kV in a 0.35-mu m silicide CMOS process by using neither the ESD-implantation nor the silicide-blocking process modifications.
ESD implantations for on-chip ESD protection with layout consideration in 0.18-mu m salicided CMOS technology
(2005-05-01)
Ker, MD
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Chuang, CH
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Lo, WY
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電機學院
;
College of Electrical and Computer Engineering
One method to enhance electrostatic discharge (ESD) robustness of the on-chip ESD protection devices is through process design by adding an extra "ESD implantation" mask. In this work, ESD robustness of nMOS devices and diodes with different ESD implantation solutions in a 0.18 mu m salicided CMOS process is investigated by experimental testchips. The second breakdown current (I-t2) of the nMOS devices with these different ESD implantation solutions for on-chip ESD protection are measured by a transmission line pulse generator (TLPG). The human-body-model (HBM) and machine-model (MM) ESD levels of these devices are also investigated and compared. A significant improvement in ESD robustness is observed when an nMOS device is fabricated with both boron and arsenic ESD implantations. The ESD robustness of the N-type diode under the reverse-biased stress condition can also be improved by the boron ESD implantation. The layout consideration in multifinger MOSFETs and diodes for better ESD robustness is also investigated.
ESD protection design for 900-MHz RF receiver with 8-kV HBM ESD robustness
(2002-01-01)
Ker, MD
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Lo, WY
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Lee, CM
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Chen, CP
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Kao, HS
This paper presents a state-of-art ESD protection design for RF circuit with a human-body-model (HBAP ESD robustness of 8kV. By including a turn-on efficient power-rails clamp circuit into the RF circuit, the ESD clamp devices of the RF input pin are operated in the forward-biased conduction, rather than the traditional junction breakdown condition Therefore, the dimension of ESD devices for the RF input pin can be further downsized to reduce the input capacitance loading for the RF signal This design has been successfully applied in a 900-MHz RF receiver and fabricated in 0.25-mum CMOS process with a thick top metal layer. The experimental results have confirmed that its ESD robustness is as high as >8kV under the HBM ESD test.
ESD protection design for 900-MHz RF receiver with 8-kV HBM ESD robustness
(2002)
Ker, MD
;
Lo, WY
;
Lee, CM
;
Chen, CP
;
Kao, HS
This paper presents a state-of-art ESD protection design for RF circuit with a human-body-model (HBM) ESD robustness of ME By including a turn-on efficient power-rails clamp circuit into the RF circuit, the ESD clamp devices of the RF input pin are operated in the forward-biased conduction, rather than the traditional junction breakdown condition. Therefore, the dimension of ESD devices for the RF input pin can be further downsized to reduce the input capacitance loading for the RF signal. This design has been successfully applied in a 900-MHz RF receiver and fabricated in 0.25-mum CMOS process with a thick top metal layer. The experimental results have confirmed that its ESD robustness is as high as >8kV under the HBM ESD test.
ESD protection design for mixed-voltage I/O circuit with substrate-triggered technique in sub-quarter-micron CMOS process
(2002)
Ker, MD
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Chuang, CH
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Hsu, KC
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Lo, WY
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電子工程學系及電子研究所
A substrate-triggered technique is proposed to improve ESD Protection efficiency of the stacked-NMOS device in the mixed-voltage I/O circuit. The substrate-triggered technique can further lower the trigger voltage of the stacked-NMOS device to ensure effective ESD protection for the mixed-voltage I/O circuit. The proposed ESD protection circuit with the substrate-triggered technique for 2.5V/3.3V tolerant mixed-voltage I/O circuit has been fabricated and verified in a 0.25-mum salicided CMOS process. Experimental results have confirmed that the HBM ESD robustness of the mixed-voltage I/O circuit can be increased similar to 65% by this substrate-triggered design.
Exact solution of inventory replenishment policy for a linear trend in demand - two-equation model
(2002-03-21)
Lo, WY
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Tsai, CH
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Li, RK
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工業工程與管理學系
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Department of Industrial Engineering and Management
This study presents a model for obtaining the exact optimal solution of inventory replenishment policy problem. The proposed model, called the "two-equation model", includes two governing equations and a time-frequency algorithm: the first equation determines the optimal replenishment times for a specified number of replenishments; the second equation determines the optimal number of replenishments. The time-frequency algorithm includes two main procedures to solve the first and second equations. In contrast to many approximation approaches, this model exactly solves the first equation, a simultaneous non-linear equations system using a generalized matrix-based solver. This study also examines the classical no-shortage inventory replenishment policy for linear increasing and decreasing trend demand. According to these results, the solution given by the two-equation model is an exact solution. (C) 2002 Elsevier Science B.V. All rights reserved.
Layout design on multi-finger MOSFET for on-chip ESD protection circuits in a 0.18-mu m salicided CMOS process
(2001)
Ker, MD
;
Chuang, CH
;
Lo, WY
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
The layout design to improve uniform ESD current distribution in multi-finger MOSFET devices for better ESD robustness is investigated in a 0.18-mum salicided CMOS process. The multi-finger MOSFET, without adding the pick-up guard ring inserted into its source region, or with the vertical direction of power line connection, can sustain a higher ESD level, The layout of I/O cell can be drawn more compactly, but still to provide deep-submicron CMOS IC's with higher ESD robustness.
Low-voltage-triggered PNP devices for ESD protection design in mixed-voltage I/O interface with over-VDD and under-VSS signal levels
(2004)
Ker, MD
;
Chang, WJ
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Lo, WY
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
ESD protection design for mixed-voltage I/O interfaces with the low-voltage-triggered PNP (LVTPNP) devices is proposed in this paper. The LVTPNP, by inserting N+ or P+ diffusion across the junction between N-well and P-substrate of the PNP devices, is designed to protect the mixed-voltage I/O pads for signals with voltage levels higher than VDD (over-VDD) and lower than VSS (under-VSS). The experimental results in a 0.35-mum CMOS process have proven that the ESD level of the proposed LVTPNP is higher than that of the traditional PNP device.
Methodology on extracting compact layout rules for latchup prevention in deep-submicron bulk CMOS technology
(2003-05-01)
Ker, MD
;
Lo, WY
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
An experimental methodology to find area-efficient compact layout rules to prevent latchup in bulk complimentary metal-oxide-semiconductor (CMOS) integrated circuits (ICs) is proposed. The layout rules are extracted from the test patterns with different layout spacings or distances, A new latchup prevention design by adding the additional internal double guard rings between input/output cells and internal circuits is first reported in the literature, and its effectiveness has been successfully proven in three different bulk CMOS processes. I Through detailed experimental verification including temperature effect, the proposed methodology to extract compact layout rules has been established to save silicon area of CMOS ICs but still to have high enough latchup immunity. This proposed methodology has been successfully verified in a 0.5-mum nonsilicided, a 0.35-mum silicided, and a 0.25-mum silicided shallow-trench-isolation bulk CMOS processes.
New diode string design with very low leakage current for using in power supply ESD clamp circuits
(2000)
Ker, MD
;
Lo, WY
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Chang, HH
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A new diode string design with very low leakage current is proposed for using in the on-chip power supply ESD electrostatic discharge) clamp circuits. Three traditional designs of the stacked diode strings used in the power supply ESD clamp circuits are also fabricated in the same test chip to verify the improvement of this new design. By adding an NMOS-controlled lateral SCR (NCLSCR) device into the stacked diode string, the leakage current of this new proposed diode string with 6 stacked diodes under a 5-V (3.3-V) forward bias condition can be controlled below 2.1 (1.07) nA at an environment temperature of 125 degrees C. The blocking voltage of this new diode string design with NCLSCR can be linearly adjusted by simply changing the number of the stacked diodes in the diode string for application across the power lines with different voltage levels to achieve the whole-chip ESD protection scheme.