Browsing by Author "Lo, Wei-Chung"

Now showing 1 - 9 of 9

3-D Stacked Technology of DRAM-Logic Controller Using Through-Silicon Via (TSV)
(2018-01-01)
Shen, Wen-Wei
;
Lin, Yu-Min
;
Chen, Shang-Chun
;
Chang, Hsiang-Hung
;
Chang, Tao-Chih
This paper describes a four-layer-stacked chip with 45-nm dynamic random access memory (DRAM) dice and 65-nm logic controller, which are interconnected by backside-via-last through-silicon via (TSV) processes. Fabrication of backside-via-last process and multiple die stacking using chip-to-chip bonding are presented with electrical connection between TSV (5-mu m-diameter/ 50-mu m-length) and Cu interconnects. Excellent fabrication of stacked dice verified that the micro bumps with 12-mu m diameter are bonded using three step temperature bonding profile. Further stacked DRAM/ Logic performance and system verifications are demonstrated successfully using 3-D heterogeneous integration.
A Comprehensive Modeling Framework for Ferroelectric Tunnel Junctions
(2019-01-01)
Huang, Hsin-Hui
;
Wu, Tzu-Yun
;
Chu, Yueh-Hua
;
Wu, Ming-Hung
;
Hsu, Chien-Hua
A modeling framework for ferroelectric tunnel junctions (FTJs) that considers nonpolar interfacial layers (ILs), multi-domain polarization, and complete ferroelectric/capacitive/tunneling currents simultaneously is proposed. This model explains both read and write operations including the controversial switching polarities of FTJ. We also provide useful guidelines for optimizing FTJ performance where the location of IL and the effective thickness ratio between ferroelectric and interfacial layers are found to be most critical.
A Novel 3D Integration Scheme for Backside Illuminated CMOS Image Sensor Devices
(2014-06-01)
Ko, Cheng-Ta
;
Hsiao, Zhi-Cheng
;
Chang, Hsiang-Hung
;
Lyu, Dian-Rong
;
Hsu, Chao-Kai
A novel backside-illuminated CMOS image sensor (BSI-CIS) scheme and process are developed and demonstrated. This innovative scheme can be realized without fusion oxide bonding and through-silicon via (TSV) fabrication. This wafer-level TSV-less BSI-CIS scheme includes transparent ultrathin silicon (similar to 3.6 mu m) and uses several bonding technologies. The characterization and assessment results indicate that the integration scheme possesses excellent electrical integrity and reliability. In addition, good quality results of the image functional test demonstrate the excellent performance of this scheme. This novel scheme also provides a realizable low-cost solution for the next-generation CIS and further 3-D novel BSI-CIS scheme.
A Wafer-Level Three-Dimensional Integration Scheme With Cu TSVs Based on Microbump/Adhesive Hybrid Bonding for Three-Dimensional Memory Application
(2012-06-01)
Ko, Cheng-Ta
;
Hsiao, Zhi-Cheng
;
Chang, Yao-Jen
;
Chen, Peng-Shu
;
Hwang, Yu-Jiau
Thin wafer/chip stacking with vertical interconnect by a Cu through-silicon via (TSV) and a Cu/Sn microjoint is one of the candidates for 3-D integration. The insertion loss of the two-chip stack was evaluated with different TSV pitches, microbump diameters, and chip thicknesses to realize the signal transmission effects in high-speed digital signaling via TSV and microjoint interconnection. In addition, a wafer-level 3-D integration scheme with Cu TSVs based on Cu/Sn microbump and BCB adhesive hybrid bonding was demonstrated. Key technologies, including TSV interconnection, microbumping, hybrid bonding, wafer thinning, and backside RDL formation, were well developed and integrated to realize 3-D integration. This paper presents a complete study of the structure design, the process condition, and the electrical and reliability assessment of the wafer-level 3-D integration scheme. This 3-D integration scheme with excellent electrical performance and reliability provides a promising solution for 3-D memory application.
Adhesive Selection and Bonding Parameter Optimization for Hybrid Bonding in 3D Integration
(2012-03-01)
Chen, Kuan-Neng
;
Ko, Cheng-Ta
;
Hsiao, Zhi-Cheng
;
Fu, Huan-Chun
;
Lo, Wei-Chung
Hybrid bonding, an emerging bonding approach with high yield and reliability, can achieve vertical interconnection with adhesive serving reinforcement of the mechanical stability between stacked ICs. To develop metal/adhesive hybrid bonding technology, four kinds of polymer materials, BOB, SU-8, AL-Polymer, and PI, were evaluated as the bonding adhesive. The compatibility between each polymer and metal was investigated, and the application range of each material was established thereof. Furthermore, the scheme of Cu-Sn-Cu interconnection hybridized with patterned BCB was designed and evaluated. Two key factors were discussed and optimized to perform the bonding integrity. The evaluation results and successful metal/adhesive hybrid bonding demonstration are disclosed in the paper.
Electrical Investigation and Reliability of 3D Integration Platform using Cu TSVs and Micro-Bumps with Cu/Sn-BCB Hybrid Bonding
(2013)
Chang, Yao-Jen
;
Ko, Cheng-Ta
;
Hsiao, Zhi-Cheng
;
Chiang, Cheng-Hao
;
Fu, Huan-Chun
In this paper, the wafer-level three-dimensional (3-D) integration scheme using copper TSVs and fine-pitch Cu/Sn-BCB hybrid bonding is designed, fabricated, and completely investigated on electrical characteristics and stability. Key technologies in this 3D integration scheme include high aspect-ratio Cu TSV, fine-pitch Cu/Sn micro-bumps, 250 degrees C low temperature hybrid bonding, wafer thinning and backside RDL formation. The Kelvin and leakage current structures are designed for realization of fundamental electrical properties, and the daisy chain feature is designed for stability evaluation with several reliability tests. All the samples pass the 1000-cycle thermal cycling test, humidity test, and multiple AC current stressing. This scheme shows a significant leakage current improvement after modifying backside process. The stable reliability results and excellent electrical characteristics indicate that the 3D integration scheme has the excellent sealing ability against oxidation and corrosion, and could be potentially applied for future mass production.
Monolithic 3D BEOL FinFET switch arrays using location-controlled-grain technique in voltage regulator with better FOM than 2D regulators
(2019-01-01)
Hsieh, Ping-Yi
;
Chang, Yi-Jui
;
Chen, Pin-Jun
;
Chen, Chun-Liang
;
Yang, Chih-Chao
Monolithic 3D back-end of line (BEOL) FinFET switch arrays are demonstrated in large single crystalline Si islands (2.56 mu m(2)), whose location, size and shape are determined by design. Details of the improved location-controlled-grain (LCG) technique are presented. A voltage regulator implemented with the BEOL switch arrays using external control signals shows better theoretical figure of merit (FOM) of 0.089ns than 2D voltage regulators of 0.43ns.
Transient Thermal Damage Simulation for Novel Location-Controlled Grain Technique in Monolithic 3D IC
(2019-01-01)
Chen, Pin-Jun
;
Shen, Chih-Ming
;
Yang, Chih-Chao
;
Tai, Ming-Chi
;
Lo, Wei-Chung
In this research, Finite Element Method (FEM) is used to simulate transient thermal conduction in the monolithic three-dimensional integrated circuit (3DIC) with a novel location-controlled-grain (LCG) technique. Through this method, the impact of laser flux, amorphous Si thickness and interlayer dielectric (ILD) thickness on that model can be investigated. Furthermore, with the assistance of thermal damage simulation, we can utilize the optimal process parameters in this state-of-the-art technique to accelerate the development of advanced semiconductor technologies.
Ultrathin Glass Wafer Lamination and Laser Debonding to Enable Glass Interposer Fabrication
(2015)
Shen, Wen-Wei
;
Chang, Hsiang-Hung
;
Wang, Jen-Chun
;
Ko, Cheng-Ta
;
Tsai, Leon
Interposer fabrication processes are applied in three-dimensional (3-D) integrated circuit (IC) integration to shorten the interconnection among different stacked chips and substrates. Because Si is a common material in semiconductor technology, Si interposers have been widely studied in many research activities. Compared with a Si wafer, glass substrates have the advantages of high resistivity, low dielectric constant, low insertion loss, adjustable coefficient of thermal expansion (CTE), and the possibility to use panel-size substrates as well as thin glass substrates (100 mu m) to avoid the costly thinning process for realization of low-cost 2.5-D ICs. Thus, glass interposer fabrication is studied thoroughly in this paper. Thin glass wafers have reduced mechanical stiffness. Therefore, handling and shipping thin glass wafers (<= 100 mu m) throughout the semiconductor fabrication and packaging assembly processes are critical. Temporary wafer bonding technology is used in this study to bond a thin glass wafer to a carrier to improve the rigidity. Vacuum lamination technology is used in this study as a bonding process to enhance the cost-effectiveness. After processing, the carrier is removed by laser debonding. The thin glass wafer with structures on both sides does not need to undergo a glass thinning process and saves a lot of cost compared to the traditional glass or Si interposer processes. Thin 300-mm glass wafers 100 mu m thick are evaluated as: (a) blank thin glass wafers and (b) thin glass wafers with through-glass vias (TGVs) 30 mu m in diameter. A UV laser with a wavelength of 308 nm, which has the benefit of less impact to the device, was adopted to laser debonding. This method also has several benefits such as high throughput, low temperature, zero-force debonding, and possible selective laser debonding. Adhesive and release layers are key enabling materials for thin glass handling. In addition, the use of a laminator for temporary bonding and laser debonding are included in this study. Based on the excellent fabrication, the thin glass interposer has great potential to be applied in 2.5-D integration applications.