Browsing by Author "Lo, Wen-Hung"

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A Method to Determine the Located Region of Lateral Trap Position by Analysis of Three-Level Random Telegraph Signals in n-MOSFETs
(2015-01-01)
Chen, Ching-En
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Chang, Ting-Chang
;
You, Bo
;
Tsai, Jyun-Yu
;
Lo, Wen-Hung
This paper introduces a method to determine the located region of trap position by the analysis of three-level random telegraph signal (RTS) in partially-depleted silicon-on-insulator n-channel metal-oxide-semiconductor field-effect-transistors. For the cases of two traps, the average time at the 2nd level ((12)) is composed of average emission time of one trap and average capture time of the other. Comparison and analysis of (tau(2)) curves varying with gate voltage in RTS measurements with and without interchanged source/drain can clarify the located regions of the two traps. Moreover, the simplified equations are also considered and used to confirm the trap positions. (C) 2015 The Electrochemical Society. All rights reserved.
Abnormal interface state generation under positive bias stress in TiN/HfO2 p-channel metal-oxide-semiconductor field effect transistors
(2012-09-24)
Lo, Wen-Hung
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Chang, Ting-Chang
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Tsai, Jyun-Yu
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Dai, Chih-Hao
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Chen, Ching-En
This Letter studies positive bias stress-induced abnormal interface state on TiN/HfO2 p-channel metal-oxide-semiconductor field effect transistors. It can be found that the degradation is associated with electron trapping, resulting in V-th shift but without subthreshold slope degradation. However, charge pumping current (I-CP) shows a significant degradation after stress. Accordingly, the impact ionization-induced Nit located HfO2/SiO2 is proposed to demonstrate the ICP degradation. The AC stress with several frequencies is used to evidence the occurrence of impact ionization. Further, the device with additional pre-existing N-it located SiO2/Si has insignificant degradation due to reduction in stress electric field. (C) 2012 American Institute of Physics. [http://dx.doi.org/10.1063/1.4752456]
Abnormal sub-threshold swing degradation under dynamic hot carrier stress in HfO2/TiN n-channel metal-oxide-semiconductor field-effect-transistors
(2013-07-08)
Tsai, Jyun-Yu
;
Chang, Ting-Chang
;
Lo, Wen-Hung
;
Chen, Ching-En
;
Ho, Szu-Han
This work finds abnormal sub-threshold swing (S.S.) degradation under dynamic hot carrier stress (HCS) in n-channel metal-oxide-semiconductor field-effect-transistors with high-k gate dielectric. Results indicate that there is no change in S.S. after dynamic HCS due to band-to-band hot hole injection at the drain side which acts to diminish the stress field. Moreover, the impaired stress field causes the interface states to mainly distribute in shallow states. This results in ON state current and transconductance decreases, whereas S.S. degradation is insignificant after dynamic HCS. The proposed model is confirmed by one-side charge pumping measurement and gate-to-drain capacitance at varying frequencies. (C) 2013 AIP Publishing LLC.
Abnormal threshold voltage shift under hot carrier stress in Ti1-xNx/HfO2 p-channel metal-oxide-semiconductor field-effect transistors
(2013-09-28)
Tsai, Jyun-Yu
;
Chang, Ting-Chang
;
Lo, Wen-Hung
;
Ho, Szu-Han
;
Chen, Ching-En
This work investigates the channel hot carrier (CHC) effect in HfO2/Ti1-xNx p-channel metal oxide semiconductor field effect transistors (p-MOSFETs). Generally, the subthreshold swing (S. S.) should increase during CHC stress (CHCS), since interface states will be generated near the drain side under high electric field due to drain voltage (V-d). However, our experimental data indicate that S. S. has no evident change under CHCS, but threshold voltage (V-th) shifts positively. This result can be attributed to hot carrier injected into high-k dielectric near the drain side. Meanwhile, it is surprising that such V-th degradation is not observed in the saturation region during stress. Therefore, drain-induced-barrier-lowering (DIBL) as a result of CHC-induced electron trapping is proposed to explain the different V-th behaviors in the linear and saturation regions. Additionally, the influence of different nitrogen concentrations in HfO2/Ti1-xNx p-MOSFETs on CHCS is also investigated in this work. Since nitrogen diffuses to SiO2/Si interface induced pre-N-it occurring to degrades channel mobility during the annealing process, a device with more nitrogen shows slightly less impact ionization, leading to insignificant charge trapping-induced DIBL behavior. (C) 2013 AIP Publishing LLC.
Analysis of an anomalous hump in gate current after dynamic negative bias stress in HfxZr1-xO2/metal gate p-channel metal-oxide-semiconductor field-effect transistors
(1970-01-01)
Ho, Szu-Han
;
Chang, Ting-Chang
;
Wu, Chi-Wei
;
Lo, Wen-Hung
;
Chen, Ching-En
"This letter investigates a hump in gate current after dynamic negative bias stress (NBS) in HfxZr1-xO2/metal gate p-channel metal-oxide-semiconductor field-effect transistors. By measuring gate current under initial through body floating and source/drain floating, it shows that hole current flows from source/drain. The fitting of gate current-gate voltage characteristic curve demonstrates that Frenkel-Poole mechanism dominates the conduction. Next, by fitting the gate current after dynamic NBS, in the order of Frenkel-Poole then tunneling, the Frenkel-Poole mechanism can be confirmed. These phenomena can be attributed to hole trapping in high-k bulk and the electric field formula Ehigh-k epsilon(high-k) = Q + E-sio2 epsilon(sio2). (C) 2012 American Institute of Physics. [http://dx.doi.org/10.1063/1.4739525]"
Analysis of anomalous traps measured by charge pumping technique in HfO2/metal gate n-channel metal-oxide-semiconductor field-effect transistors
(2012-12-03)
Ho, Szu-Han
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Chang, Ting-Chang
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Lu, Ying-shin
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Lo, Wen-Hung
;
Chen, Ching-En
This letter investigates anomalous traps measured by charge pumping technique in high voltage in HfO2/metal gate n-channel metal-oxide-semiconductor field-effect transistors. N-V-high level characteristic curves with different duty ratios indicate that the electron discharge time dominates the value of N for extra traps. By fitting ln (N (t(base level) = 2.5 mu s)-N (t(base level)))-Delta t(base level) at different temperatures and computing the equation t = tau(0) exp (alpha(e,SiO2)d(SiO2) + alpha(e,HfO2)d(HfO2,trap)), results show that these extra traps measured by the charge pumping technique at high voltage can be attributed to high-k bulk shallow traps. (C) 2012 American Institute of Physics. [http://dx.doi.org/10.1063/1.4769444]
Analysis of Oxide Trap Characteristics by Random Telegraph Signals in nMOSFETs With HfO2-Based Gate Dielectrics
(2016-04)
Chen, Ching-En
;
Chang, Ting-Chang
;
You, Bo
;
Tsai, Jyun-Yu
;
Lo, Wen-Hung
This letter investigates the oxide trap properties in n-channel metal-oxide-semiconductor field-effect transistors with HfO2 and Hf(1-x)ZrxO(2)/metal gate-stacks by an analysis of random telegraph signals. According to the multiphonon emission theory, the extracted relaxation energies show gate voltage dependence in devices with HfO2-based stacks. This dependence results from the different strengths of vibrations of the nearest neighbor Hf atoms of the oxygen vacancy in the immediate vicinity of the oxide trap. Furthermore, this dependence also induces an abnormal gate voltage dependence in terms of the activation energy required for electron capture. These results are confirmed by comparisons between two HfO2-based devices (HfO2 and Hf(1-x)ZrxO(2)).
Anomalous Gate Current Hump after Dynamic Negative Bias Stress and Negative-Bias Temperature-Instability in p-MOSFETs with HfxZr1-xO2 and HfO2/Metal Gate Stacks
(2013)
Ho, Szu-Han
;
Chang, Ting-Chang
;
Wu, Chi-Wei
;
Lo, Wen-Hung
;
Chen, Ching-En
In this study, the authors investigated an anomalous gate current hump after dynamic negative bias stress (NBS) and negative-bias temperature-instability (NBTI) in HfxZr1-xO2 and HfO2/metal gate p-channel metal-oxide-semiconductor field-effect transistors. This result is attributed to hole trapping in high-k bulk. Measuring gate current under initial through body floating and source/drain floating conditions indicates that holes flow from source/drain to gate. The fitting of the gate current-gate voltage characteristic curve demonstrates that Frenkel-Poole mechanism dominates the conduction under initial. Next, fitting the gate current after dynamic NBS and NBTI indicates Frenkel-Poole then tunneling mechanisms, finally returning to the Frenkel-Poole mechanism. These phenomena can be attributed to hole trapping in high-k bulk and the formula Ehigh-k epsilon(high-k) = Q + E-sio2 epsilon(sio2). To further understand the gate current hump, both Zr-undoped and 8 similar to 10% Zr-doped in high-k bulk devices were used for comparisons. These results indicate that initial gate current is also a significant factor in generating the anomalous gate current hump, and all results obey the hump generation condition of J(Tunneling) << J(Frenkel-Poole). (C) 2013 The Electrochemical Society. All rights reserved.
Charge trapping induced drain-induced-barrier-lowering in HfO2/TiN p-channel metal-oxide-semiconductor-field-effect-transistors under hot carrier stress
(2012-04-09)
Lo, Wen-Hung
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Chang, Ting-Chang
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Tsai, Jyun-Yu
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Dai, Chih-Hao
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Chen, Ching-En
This letter studies the channel hot carrier stress (CHCS) behaviors on high dielectric constant insulator and metal gate HfO2/TiN p-channel metal-oxide-semiconductor field effect transistors. It can be found that the degradation is associated with electron trapping, resulting in G(m) decrease and positive Vth shift. However, Vth under saturation region shows an insignificant degradation during stress. To compare that, the CHC-induced electron trapping induced DIBL is proposed to demonstrate the different behavior of Vth between linear and saturation region. The devices with different channel length are used to evidence the trapping-induced DIBL behavior. (C) 2012 American Institute of Physics. [http://dx.doi.org/10.1063/1.3697644]
Charge trapping induced frequency-dependence degradation in n-MOSFETs with high-k/metal gate stacks
(2011-12-30)
Dai, Chih-Hao
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Chang, Ting-Chang
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Chu, Ann-Kuo
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Kuo, Yuan-Jui
;
Hung, Ya-Chi
This letter investigates the reliability issues of HfO(2)/Ti(1-x)N(x) metal-oxide-semiconductor field effect transistor in terms of static and dynamic stress. The results indicate threshold voltage (V(th)) instability under dynamic stress is more serious than that under static stress, owning to transient charge trapping within high-k dielectric. Capacitance-voltage techniques verified that electron trapping under dynamic stress was located in high-k dielectric near the source/drain (S/D) overlap region, rather than the overall dielectric. Furthermore, the V(th) shift clearly increases with an increase in dynamic stress operation frequency. This phenomenon can be attributed to the fact that electrons injecting to the S/D overlap region have insufficient time to de-trap from high-k dielectric. We further investigated the impact of different Ti(1-x)N(x) composition of metal-gate electrode on charge trapping characteristics, and observed that V(th) shift decreases significantly with an increase in the ratio of nitride. This is because the nitride atoms diffusing from the metal gate fill up oxygen vacancies and reduce the concentration of traps in high-k dielectric. Crown Copyright (C) 2011 Published by Elsevier B.V. All rights reserved.
Enhanced gate-induced floating-body effect in PD SOI MOSFET under external mechanical strain
(2010-11-25)
Dai, Chih-Hao
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Chang, Ting-Chang
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Chu, Ann-Kuo
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Kuo, Yuan-Jui
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Chen, Shih-Ching
The influence of tensile mechanical strain on gate-induced floating-body effect (GIFBE) in advanced partially depleted SOI n-MOSFETs was investigated. Both drain current and mobility enhance after applying strain due to the reduction of average transfer effective mass. However, it was found that the GIFBE becomes serious under the mechanical strain. To explain this phenomenon, we first clarify the mechanism of GIFBE using different operation conditions. The experiment results indicate that the GIFBE can be attributed to the anode hole injection (AHI) rather than the widely accepted mechanism of electron band (EVB) tunneling. Based on the AHI model, the enhanced GIFBE under the mechanical strain is mainly due to the narrowing of band gap induced by the strain in the poly-gate. (C) 2010 Elsevier B.V. All rights reserved.
High-k shallow traps observed by charge pumping with varying discharging times
(2013-11-07)
Ho, Szu-Han
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Chang, Ting-Chang
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Lu, Ying-Hsin
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Wang, Bin-Wei
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Lo, Wen-Hung
In this paper, we investigate the influence of falling time and base level time on high-k bulk shallow traps measured by charge pumping technique in n-channel metal-oxide-semiconductor field-effect transistors with HfO2/metal gate stacks. N-T-V-high level characteristic curves with different duty ratios indicate that the electron detrapping time dominates the value of N-T for extra contribution of I-cp traps. N-T is the number of traps, and I-cp is charge pumping current. By fitting discharge formula at different temperatures, the results show that extra contribution of I-cp traps at high voltage are in fact high-k bulk shallow traps. This is also verified through a comparison of different interlayer thicknesses and different TixN1-x metal gate concentrations. Next, N-T-V-high level characteristic curves with different falling times (t(falling time)) and base level times (t(base level)) show that extra contribution of I-cp traps decrease with an increase in t(falling time). By fitting discharge formula for different t(falling time), the results show that electrons trapped in high-k bulk shallow traps first discharge to the channel and then to source and drain during t(falling time). This current cannot be measured by the charge pumping technique. Subsequent measurements of N-T by charge pumping technique at t(base level) reveal a remainder of electrons trapped in high-k bulk shallow traps. (c) 2013 AIP Publishing LLC.
Hole injection-reduced hot carrier degradation in n-channel metal-oxide-semiconductor field-effect-transistors with high-k gate dielectric
(2013-02-18)
Tsai, Jyun-Yu
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Chang, Ting-Chang
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Lo, Wen-Hung
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Chen, Ching-En
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Ho, Szu-Han
This work finds a significant difference in degradation under hot carrier stress (HCS) due to additional hole injection in n-channel metal-oxide-semiconductor field-effect-transistors with high-k gate dielectric. A comparison performed on degradation of input/output (I/O) and standard performance (SP) devices showed that performance degradation of the I/O device is worse than the SP device under HCS. For the SP device, both channel-electrons and hot holes can inject into gate dielectric, in which hole acts to diminish the stress field. However, I/O device shows only electron injection. The proposed model is confirmed by gate induced drain leakage current and simulation tool. (C) 2013 American Institute of Physics. [http://dx.doi.org/10.1063/1.4791676]
Hot carrier effect on gate-induced drain leakage current in high-k/metal gate n-channel metal-oxide-semiconductor field-effect transistors
(2011-07-04)
Dai, Chih-Hao
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Chang, Ting-Chang
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Chu, Ann-Kuo
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Kuo, Yuan-Jui
;
Ho, Szu-Han
This paper investigates the channel hot carrier stress (CHCS) effects on gate-induced drain leakage (GIDL) current in high-k/metal-gate n-type metal-oxide-semiconductor field effect transistors. It was found that the behavior of GIDL current during CHCS is dependent upon the interfacial layer (IL) oxide thickness of high-k/metal-gate stacks. For a thinner IL, the GIDL current gradually decreases during CHCS, a result contrary to that found in a device with thicker IL. Based on the variation of GIDL current at different stress conditions, the trap-assisted band-to-band hole injection model is proposed to explain the different behavior of GIDL current for different IL thicknesses. (C) 2011 American Institute of Physics. [doi:10.1063/1.3608241]
Hot Carrier Effect on Gate-Induced Drain Leakage Current in n-MOSFETs with HfO2/Ti1-xNx Gate Stacks
(2012)
Dai, Chih-Hao
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Chang, Ting-Chang
;
Chu, Ann-Kuo
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Kuo, Yuan-Jui
;
Ho, Szu-Han
"This paper investigates the effect of channel hot carrier stress (CHCS) on gate-induced drain leakage (GIDL) current in n-type metal-oxide-semiconductor field effect transistor (n-MOSFETs) with HfO2/Ti1-xNx gate stacks. It was found that the behavior of GIDL current during CHCS has dependence with the interfacial layer (IL) oxide thickness of high-k/metal gate stacks. As IL thickness becomes thinner, the GIDL current has a gradual decrease during CHCS, which is contrary to the result of thick-oxide IL devices. Based on the variation of GIDL current (Delta I-GIDL) in different stress voltage across gate and drain terminals, trap-assisted band to band holes injection model was proposed to explain the different behavior of GIDL current for different IL thickness. Furthermore, we also investigated the impact of different Ti1-xNx composition of metal gate electrode on the Delta I-GIDL after CHCS, and observed that the magnitude of Delta I-GIDL decreases with the increase of nitride ratio. This is due to the fact that nitride atoms diffusing from the metal gate fill up oxygen vacancies, and reduce the concentration of traps in high-k dielectric. (C) 2012 The Electrochemical Society. [DOI: 10.1149/2.001206esl] All rights reserved."
Impact of static and dynamic stress on threshold voltage instability in high-k/metal gate n-channel metal-oxide-semiconductor field-effect transistors
(2011-02-28)
Dai, Chih-Hao
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Chang, Ting-Chang
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Chu, Ann-Kuo
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Kuo, Yuan-Jui
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Lo, Wen-Hung
This letter investigates the impact of static and dynamic stress on threshold voltage (V(th)) instability in ultrathin n-channel metal-oxide-semiconductor field-effect transistors with hafnium-based gate stacks. Experimental results indicate V(th) shift under dynamic stress is more serious than that under static stress due to charge trapping within the high-k dielectric. Capacitance-voltage techniques demonstrated that electron trapping under dynamic stress was located in the high-k dielectric near the source/drain overlap region rather than throughout the overall dielectric layer. This implies in real circuit operation, the phenomenon of electrons trapped in high-k near the source/drain overlap is the main issue affecting V(th) instability. (C) 2011 American Institute of Physics. [doi:10.1063/1.3560463]
Impact of strain on gate-induced floating body effect for partially depleted silicon-on-insulator p-type metal-oxide-semiconductor-field-effect-transistors
(2013-01-15)
Lo, Wen-Hung
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Chang, Ting-Chang
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Dai, Chih-Hao
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Chung, Wan-Lin
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Chen, Ching-En
This work investigates impact of mechanical strain on gate-induced-floating-body-effect (GIFBE) for partially depleted silicon-on-insulator p-type metal-oxide-semiconductor field effect transistors (PD SOI p-MOSFETs). First part, the original mechanism of GIFBE on PD SOI p-MOSFETs is studied. The experimental results indicate that GIFBE causes a reduction in oxide electric field (E-ox), resulting in an underestimate of negative-bias temperature instability (NBTI) degradation. This can be attributed to the electrons tunneling from the process-induced partial n(+) poly gate and anode electron injection (AEI) model, rather than the electron valence band tunneling (EVB) widely accepted as the mechanism for n-MOSFETs. And then, the second part shows that the strained FB device has less NBTI degradation than the unstrained devices. This behavior can be attributed to the fact that more electron accumulation was induced by strain-induced band gap narrowing, reducing NBTI significantly. (c) 2012 Elsevier B.V. All rights reserved.
Investigation of an anomalous hump in gate current after negative-bias temperature-instability in HfO2/metal gate p-channel metal-oxide-semiconductor field-effect transistors
(2013-01-07)
Ho, Szu-Han
;
Chang, Ting-Chang
;
Wu, Chi-Wei
;
Lo, Wen-Hung
;
Chen, Ching-En
This Letter investigates a hump in gate current after negative-bias temperature-instability (NBTI) in HfO2/metal gate p-channel metal-oxide-semiconductor field-effect transistors. Measuring gate current at initial through body floating and source/drain floating shows that hole current flows from source/drain. The fitting of gate current (I-g)-gate voltage (V-g) characteristic curves demonstrates that the Frenkel-Poole mechanism dominates the conduction. Next, by fitting the gate current after NBTI, in the order of Frenkel-Poole then tunneling, the Frenkel-Poole mechanism can be confirmed. These phenomena can be attributed to hole trapping in high-k bulk and the electric field formula Ehigh-k epsilon(high-k) = Q+E-sio2 epsilon(sio2). (C) 2013 American Institute of Physics. [http://dx.doi.org/10.1063/1.4773479]
Investigation of extra traps measured by charge pumping technique in high voltage zone in p-channel metal-oxide-semiconductor field-effect transistors with HfO2/metal gate stacks
(2013-01-07)
Ho, Szu-Han
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Chang, Ting-Chang
;
Wang, Bin-Wei
;
Lu, Ying-Shin
;
Lo, Wen-Hung
This letter investigates extra traps measured by charge pumping technique in the high voltage zone in p-channel metal-oxide-semiconductor field-effect transistors with HfO2/metal gate stacks. N-V-high level characteristic curves with different duty ratios show that the hole discharge time (t(base level)) dominates the value of extra traps. By fitting ln (N (t(base level) = 1 mu s) -N (t(base level))) - Delta t(base level) at different temperatures and computing the equation t = tau(0) exp (alpha(h,SiO2)d(SiO2) + alpha(h,HfO2)d(HfO2,trap)), the results show that these extra traps measured by the charge pumping technique at high voltage zone can be attributed to high-k bulk shallow traps. (C) 2013 American Institute of Physics. [http://dx.doi.org/10.1063/1.4773914]
Investigation of Lateral Trap Position by Random Telegraph Signal Analysis in Moderate Inversion in n-Channel MOSFETs
(2013)
Chen, Ching-En
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Chang, Ting-Chang
;
You, Bo
;
Lo, Wen-Hung
;
Ho, Szu-Han
This paper investigates the trap position by random telegraph signal (RTS) analysis in moderate inversion in partially depleted silicon-on-insulator n-channel metal-oxide-semiconductor field-effect transistors. In the diffusion current-dominated region, the electron concentration distribution is more non-uniform along the channel than the one in the drift current-dominated region. In the diffusion region, the application of drain (source) voltage can influence the potential at the drain (source) side only. Accordingly, the position of oxide trap can be further clarified using RTS measurements to compare both the capture times as well as the relative channel current amplitudes of devices with and without interchanged source/drain. (C) 2013 The Electrochemical Society. All rights reserved.