Browsing by Author "Lo, Yi-Kai"

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A 3-10 GHz CMOS UWB Low-Noise Amplifier With ESD Protection Circuits
(2009-11-01)
Wu, Chung-Yu
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Lo, Yi-Kai
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Chen, Min-Chiao
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
A low-power fully integrated low-noise amplifier (LNA) with an on-chip electrostatic-static discharge (ESD) protection circuit for ultra-wide band (UWB) applications is presented. With the use of a common-gate scheme with a g(m)-boosted technique, a simple input matching network, low noise figure (NF), and low power consumption can be achieved. Through the combination of an input matching network, an ESD clamp circuit has been designed for the proposed LNA circuit to enhance system robustness. The measured results show that the fabricated LNA can be operated over the full UWB bandwidth of 3.0 to 10.35 GHz. The input return loss (S(11)) and output return loss (S(22)) are less than -8.3 dB and -9 dB, respectively. The measured power gain (S(21)) is 11 +/- 1.5 dB, and the measured minimum NF is 3.3 dB at 4 GHz. The dc power dissipation is 7.2 mW from a 1.2 V supply. The chip area, including testing pads, is 1.05 mm x 0.73 mm.
A 3.1 similar to 10.6 GHz CMOS direct-conversion receiver for UWB applications
(2006)
Wu, Chung-Yu
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Lo, Yi-Kai
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Chen, Min-Chiao
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
In this paper, a 3.1 similar to 10.6 GHz fully integrated low-power CMOS direct-conversion receiver for ultra-wideband (UWB) applications is proposed and analyzed. The proposed receiver consists of a wideband low-noise amplifier (WLNA), quadrature down-conversion mixers, output I/Q buffers and a carrier generator. This chip was designed in 0.13-um CMOS technology. According to the simulation results, the proposed receiver has noise figure (NF) of 4.1 similar to 7.1 dB, receiver voltage gain of 22 dB, and input-referred 1-dB compression point (P-1dB) of -22 similar to-26 dBm and third-order intercept point (IIP3) of -12 similar to-16 dBm. It consumes 38.4 mW from 1.2 V power supply.
A Fully Integrated Wireless SoC for Motor Function Recovery After Spinal Cord Injury
(2017-06-01)
Lo, Yi-Kai
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Kuan, Yen-Cheng
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Culaclii, Stanislav
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Kim, Brian
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Wang, Po-Min
This paper presents a wirelessly powered, fully integrated system-on-a-chip (SoC) supporting 160-channel stimulation, 16-channel recording, and 48-channel bio-impedance characterization to enable partialmotor function recovery through epidural spinal cord electrical stimulation. A wireless transceiver is designed to support quasi full-duplex data telemetry at a data rate of 2 Mb/s. Furthermore, a unique in situ bio-impedance characterization scheme based on time-domain analysis is implemented to derive the Randles cell electrode model of the electrode-electrolyte interface. The SoC supports concurrent stimulation and recording while the high-density stimulator array meets an output compliance voltage of up to +/- 10 V with versatile stimulus programmability. The SoC consumes 18 mW and occupies a chip area of 5.7 mm x 4.4 mm using 0.18 mu m high-voltage CMOS process. In our in vivo rodent experiment, the SoC is used to perform wireless recording of EMG responses while stimulation is applied to enable the standing and stepping of a paralyzed rat. To facilitate the system integration, a novel thin film polymer packaging technique is developed to provide a heterogeneous integration of the SoC, coils, discrete components, and high-density flexible electrode array, resulting in a miniaturized prototype implant with a weight and form factor of 0.7 g and 0.5 cm(3), respectively.
A Phase-Locked Loop With Injection-Locked Frequency Multiplier in 0.18-mu m CMOS for V-Band Applications
(2009-07-01)
Wu, Chung-Yu
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Chen, Min-Chiao
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Lo, Yi-Kai
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電機學院
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College of Electrical and Computer Engineering
In this paper, a novel CMOS phase-locked loop (PLL) integrated with an injection-locked frequency multiplier (ILFM) that generates the V-band output signal is proposed. Since the proposed ILFM can generate the fifth-order harmonic frequency of the voltage-controlled oscillator (VCO) output, the operational frequency of the VCO can be reduced to only one-fifth of the desired frequency. With the loop gain smaller than unity in the ILFM, the output frequency range of the proposed PLL is from 53.04 to 58.0 GHz. The PLL is designed and fabricated in 0.18-mu m CMOS technology. The measured phase noises at 1- and 10-MHz offset from the carrier are -85.2 and -90.9 dBc/Hz, respectively. The reference spur level of -40.16 dBc is measured. The dc power dissipation of the fabricated PLL is 35.7 mW under a 1.8-V supply. It can be seen that the advantages of lower power dissipation and similar phase noise can be achieved in the proposed PLL structure. It is suitable for low-power and high-performance V-band applications.
The design of integrated 3-GHz to 11-GHz CMOS transmitter for full-band ultra-wideband (UWB) applications
(2008)
Wang, Wen-Chieh
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Liao, Chang-Ping
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Lo, Yi-Kai
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Huang, Zue-Der
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Shahroury, Fadi R.
The CMOS integrated 3-GHz to 11-GHz transmitter for full-band UWB applications is proposed and designed in 0.13-mu m CMOS technology. The designed UWB transmitter is integrated with a 2:1 frequency divider, a quadrature up-conversion mixer, a balanced RF amplifier, and a 3-stage cascaded poly-phase filter. The technique of inductance peaking has been adopted to achieve 14-band operation for UWB applications. The transmitter has an average conversion gain of 12.8 dB with the gain ripple of around +/- 1.4 dB among the whole frequency band. The average input 1-dB compression point (IP(-1dB)) of the 14 bands is -12.2 dBm and the average output 1-dB compression point (OP-(1dB)) of the 14 bands is -0.4 dBm. The transmitter dissipates the power of 53.1 mW from the supply 2 voltage of 1.2 V and occupies the chip area of 1930X1635 mu m(2). This chip is designed in 0.13-mu m 1P8M CMOS technology and under fabrication.