Browsing by Author "Lou, DC"

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Parallel distance transforms on a linear array architecture
(2002-04-30)
Chia, TL
;
Wang, KB
;
Chen, Z
;
Lou, DC
;
資訊科學與工程研究所
Distance transformation (DT) has been widely used for image matching and shape analysis. In this paper, a parallel algorithm for computing distance transformation is presented. First, it is shown that the algorithm has an execution time of 6N - 4 cycles, for an N x N image using a parallel architecture that requires [N/2] parallel processors. By doing so, the real time requirement is fulfilled and its execution time is independent of the image contents. In addition, a partition method is developed to process an image when the parallel architecture has a fixed number of processing elements (PEs); say two or more. The total execution time for an N x N image by employing a fixed number of PEs is 2[N-2/M + 2(M - 1)], when M is the fixed number of PEs. (C) 2002 Elsevier Science B.V. All rights reserved.
Parallel execution of a connected component labeling operation on a linear array architecture
(2003-03-01)
Wang, KB
;
Chia, TL
;
Chen, Z
;
Lou, DC
;
資訊科學與工程研究所
This work presents a novel parallel algorithm and architecture for finding connected components in an image. Simulation results indicate that the proposed algorithm has an execution time of N-2 +6N-4 cycles for an NxN image using an architecture containing 4 parallel processors. The proposed hardware can process a 128 x 128 image in 0.8574 ms and uses only 4 processors, compared to 0.85 ms and 128 processors for the work of Ranganathan et al. [14], and 94.6 ms and 16384 processors for the MPP [22]. Among the advantages of the novel architecture are modularity, expandability, regular data flow, and simple hardware. These properties are extremely desirable for VLSI implementations. Additionally, the execution time of the algorithm is independent of its image content; thus, it is quite flexible.