Browsing by Author "Lou, J. C."

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Characteristics of hafnium oxide resistance random access memory with different setting compliance current
(2013-10-14)
Su, Yu-Ting
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Chang, Kuan-Chang
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Chang, Ting-Chang
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Tsai, Tsung-Ming
;
Zhang, Rui
In this Letter, the characteristics of set process of hafnium oxide based resistance random access memory are investigated by different set processes with increasing compliance current. Through current fitting, carrier conduction mechanism of low resistance state changes from hopping to surface scattering and finally to ohmic conduction with the increase of setting compliance current. Experimental data of current-voltage measurement under successive increasing temperature confirms the conduction mechanism transition. A model of filament growth is eventually proposed in a way by merging discrete metal precipitates and electrical field simulation by COMSOL Multiphysics further clarifies the properties of filament growth process. (C) 2013 AIP Publishing LLC.
Characterization of inter-poly high-kappa dielectrics for next generation stacked-gate flash memories
(2006)
Chen, Y. Y.
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Li, T. H.
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Kin, K. T.
;
Chien, C. H.
;
Lou, J. C.
In this paper, the inter-poly dielectric (IPD) thickness, scaling, and reliability characteristics of Al2O3 and HfO2 IPDs are studied, which are then compared with TEOS IPD. Regardless of deposition tools, drastically leakage current reduction and reliability improvements have been demonstrated by replacing TEOS IPD with high-permittivity (high-kappa) IPDs, which are suitable for mass production applications in the future. Moreover, MOCVD deposition can be used to further promote dielectric reliability when compared to reactive-sputtering deposition. By using MOCVD deposition, the QRD can be significantly improved, in addition to reduced leakage current density, enhanced breakdown voltage and effective breakdown field. Our results clearly demonstrate that both MOCVD-Al2O3 and MOCVD-HfO2 IPD possess great potential for next generation stacked-gate flash memories.
Dielectric properties of nitric oxide-annealed gate oxides grown on nitrogen-implanted silicon substrates
(2006-08-14)
Chen, Y. Y.
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Chien, C. H.
;
Lou, J. C.
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
The characteristics of nitric oxide (NO)-annealed nitrided gate oxides grown on nitrogen-implanted silicon substrates (NIS) were studied in this paper. It was found that nitrogen accumulation occurred near the interface after NO-annealing, while NIS-grown nitrided oxide produced a uniform nitrogen distribution in the dielectric bulk. Moreover, it was found that the dielectric reliability is strongly dependent on the dosages used for NIS preparation. NIS with dosages smaller than 10(14) cm(-2) was found not to suppress the oxidation rate and to degrade the dielectric reliability. On the other hand, the samples with a dosage of 10(15) cm(-2) not only exhibited a significantly reduced oxidation rate, making it suitable for growing oxides of multiple thicknesses in sub-3 nm technologies meeting the Systems on Chip requirement, but also improved the dielectric reliability. NO-annealed NIS-grown nitrided oxides depict superior dielectric reliability and this technique appears to be suitable to replace the traditional SiO2 at 0.13 mu m technology node and beyond. (c) 2006 Elsevier B.V. All rights reserved.
Electrical conduction mechanism of Zn:SiOx resistance random access memory with supercritical CO2 fluid process
(2013-08-19)
Chang, Kuan-Chang
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Tsai, Tsung-Ming
;
Zhang, Rui
;
Chang, Ting-Chang
;
Chen, Kai-Huang
In this study, the electrical conduction mechanism of Zn:SiOx resistance random access memory (RRAM) treated with supercritical CO2 fluid (SCCO2) process was investigated by low temperature measurement. The current of low resistance state for current-voltage curves in SCCO2-treated and untreated Zn:SiOx RRAM were measured and compared under a low temperature range from 100K to 298 K. The electrical conduction mechanisms of hopping conduction and metal-like behaviors in SCCO2-treated and untreated Zn:SiOx RRAM were discussed, respectively. Finally, the electrical conduction mechanism was analyzed and verified by the chemical composition and bonding intensity of XPS analyses. (C) 2013 AIP Publishing LLC.
Hopping conduction distance dependent activation energy characteristics of Zn:SiO2 resistance random access memory devices
(2013-04-01)
Chen, Kai-Huang
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Zhang, Rui
;
Chang, Ting-Chang
;
Tsai, Tsung-Ming
;
Chang, Kuan-Chang
In this study, the hopping conduction distance variation of Zn:SiO2 resistance random access memory (RRAM) devices with different operating compliance currents was discussed and verified. To investigate and determine the hopping conduction distance dependent activation energy characteristics, the Arrhenius plot of low resistance state of Zn:SiO2 RRAM devices was applied, from which we proposed carrier conduction model. With the increase of current compliance, more metal ions would accumulate to form precipitates with larger diameter, which in turn resulted in the shortening of hopping distance. Because of shorter hopping distance, activation energy for carrier hopping would decrease. (C) 2013 American Institute of Physics. [http://dx.doi.org/10.1063/1.4799655]
Memory characteristics of Co nanocrystal memory device with HfO(2) as blocking oxide
(2007-03-26)
Yang, F. M.
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Chang, T. C.
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Liu, P. T.
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Yeh, P. H.
;
Yu, Y. C.
In this letter, the Co nanocrystals using SiO(2) and HfO(2) as the tunneling and the control dielectric with memory effect has been fabricated. A significant memory effect was observed through the electrical measurements. Under the low voltage operation of 5 V, the memory window was estimated to similar to 1 V. The retention characteristics were tested to be robust. Also, the endurance of the memory device was not degraded up to 10(6) write/erase cycles. The processing of the structure is compatible with the current manufacturing technology of semiconductor industry. (c) 2007 American Institute of Physics.
Memory characteristics of Co nanocrystal memory device with HfO2 as blocking oxide
(2007-03-26)
Yang, F. M.
;
Chang, T. C.
;
Liu, P. T.
;
Yeh, P. H.
;
Yu, Y. C.
In this letter, the Co nanocrystals using SiO2 and HfO2 as the tunneling and the control dielectric with memory effect has been fabricated. A significant memory effect was observed through the electrical measurements. Under the low voltage operation of 5 V, the memory window was estimated to similar to 1 V. The retention characteristics were tested to be robust. Also, the endurance of the memory device was not degraded up to 10(6) write/erase cycles. The processing of the structure is compatible with the current manufacturing technology of semiconductor industry. (c) 2007 American Institute of Physics.
Nickel nanocrystals with HfO2 blocking oxide for nonvolatile memory application
(2007-05-28)
Yang, F. M.
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Chang, T. C.
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Liu, P. T.
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Chen, U. S.
;
Yeh, P. H.
A distributed charge storage with Ni nanocrystals embedded in the SiO2 and HfO2 layer has been fabricated in this study. The mean size and aerial density of the Ni nanocrystals are estimated to be about 5 nm and 3.9x10(12)/cm(2), respectively. The nonvolatile memory device with Ni nanocrystals exhibits 1 V threshold voltage shift under 4 V write operation. The device has a long retention time with a small charge lose rate. Besides, the endurance of the memory device is not degraded up to 10(6) write/erase cycles. (C) 2007 American Institute of Physics.
Nickel silicide nanocrystals embedded in SiO2 and HfO2 for nonvolatile memory application
(2007-12-03)
Yang, F. M.
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Chang, T. C.
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Liu, Po-Tsun
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Yeh, Y. H.
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Yu, Y. C.
In this study, a nonvolatile memory device with NiSi2 nanocrystals embedded in the SiO2 and HfO2 layer has been fabricated. A significant memory effect is observed during the characterization of the electrical properties. When a low operating voltage, 4 V, is applied, a significant threshold voltage shift of 1.3 V, is observed. The processing of this structure is compatible with the current manufacturing technology of semiconductor industry. (C) 2007 Published by Elsevier B.V.
Novel oxynitride layer applied to flash memory using HfO(2) as charge trapping layer
(2007)
Hsieh, C. R.
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Lai, C. H.
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Lin, B. C.
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Lou, J. C.
;
Lin, J. K.
When the thickness of tunnel oxide layer is thinner than 7nm, the defects of tunnel oxide will form the leakage path easily. The trapped charges in trapping layer leak out through the leakage path and let we read the wrong data information. Therefore, the novel oxynitride process has been proposed to improve the reliabilities of Flash memory by reducing the interface states and bulk defects. Moreover, the novel oxynitride process is compatible with standard CMOS process today and it is practicable improvement in industry manufacturing. The HfO(2) layer was used as charge trapping layer. At first we found the better PDA conditions of HfO(2) film from the test capacitors and applied the optimum condition in integrated Flash memory devices. Finally, the complete electrical measurements and analysis were carried out. From the result of this study, the oxynitride can promote the reliabilities of Flash memory by improving the quality of tunnel oxide.
Origin of Hopping Conduction in Graphene-Oxide-Doped Silicon Oxide Resistance Random Access Memory Devices
(2013-05-01)
Chang, Kuan-Chang
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Zhang, Rui
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Chang, Ting-Chang
;
Tsai, Tsung-Ming
;
Lou, J. C.
In this letter, a double-active-layer (Zr:SiOx/C:SiOx) resistive switching memory device with a high ON/OFF resistance ratio and small working current (0.02 mA), is presented. Through the analysis of Raman and Fourier transform infrared spectroscopy spectra, we find that graphene oxide exists in the C:SiOx layer. It can be observed that Zr:SiOx/C: SiOx structure has superior switching performance and higher stability compared with the single-active-layer (Zr:SiOx) structure, which is attributed to the existence of graphene oxide flakes formed during the sputter process. I-V characteristics under a series of increasing temperature were analyzed to testify the carrier hopping distance variation, which is further verified by our graphene oxide redox reaction model.
Performance and characteristics of double layer porous silicon oxide resistance random access memory
(2013-06-24)
Tsai, Tsung-Ming
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Chang, Kuan-Chang
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Zhang, Rui
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Chang, Ting-Chang
;
Lou, J. C.
A bilayer resistive switching memory device with an inserted porous silicon oxide layer is investigated in this letter. Compared with single Zr:SiOx layer structure, Zr: SiOx/ porous SiOx structure outperforms from various aspects, including low operating voltages, tighter distributions of set voltage, higher stability of both low resistance state and high resistance state, and satisfactory endurance characteristics. Electric field simulation by COMSOL (TM) Multiphysics is applied, which corroborates that intensive electric field around the pore in porous SiOx layer guides the conduction of electrons. The constraint of conduction path leads to better stabilization and prominent performance of bilayer resistive switching devices. (C) 2013 AIP Publishing LLC.
Programming efficiency of stacked-gate flash memories with high-kappa dielectrics
(2006)
Chen, Y. Y.
;
Chien, C. H.
;
Kin, K. T.
;
Lou, J. C.
;
電子工程學系及電子研究所
The programming efficiency of high-permittivity (K) inter-poly dielectrics (IPDs) and tunnel dielectrics (TDs) on the stacked-gate flash memory performance is evaluated. By 2D MEDICI simulation, stacked-gate flash memories with high-K IPDs clearly exhibited significant improvement in operation speed over those with conventional oxide/nitride/oxide IPD programmed with either channel Fowler-Nordheim (CFN) or channel hot electron (CHE) injection. Choosing HfO2 as the IPD and using CFN programming scheme, the operating voltage can be reduced by more than 48% under a typical lops programming time. However, the effect of high-kappa TDs was quite different when compared with high-K IPDs. High-kappa TDs were only beneficial for memories programmed with CHE injection instead of CFN tunneling. The operating voltage can be reduced by more than 27% under lops programming time by choosing HfO2 as both the IPD and TD with CHE programming scheme. Due to the contrary improvement in programming schemes, high-kappa IPDs and TDs were suitable for next-generation NAND-and NOR-type stacked-gate flash memories, respectively.
The effect of high/low permittivity in bilayer HfO2/BN resistance random access memory
(2013-05-20)
Huang, Jen-Wei
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Zhang, Rui
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Chang, Ting-Chang
;
Tsai, Tsung-Ming
;
Chang, Kuan-Chang
This letter investigated the electrical characteristics of resistance random access memory (RRAM) with HfO2/BN bilayer structures. By adopting the high/low permittivity structure, we obtained the excellent device characteristics such as uniform distribution of switching voltage and more stable resistance switching properties of RRAM. The current conduction mechanism of low resistance state in the HfO2/BN device was transferred to space-charge-limited current conduction from Ohmic conduction owing to space electric effect concentrated by the high/low permittivity bilayer structures. The electric field in the bilayer can be verified by COMSOL simulation software. (C) 2013 AIP Publishing LLC.
Using double layer CoSi2 nanocrystals to improve the memory effects of nonvolatile memory devices
(2007-05-21)
Yang, F. M.
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Chang, T. C.
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Liu, P. T.
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Yeh, P. H.
;
Chen, U. S.
The nonvolatile memory device with multilayer nanocrystals has advantages such as the memory effects can be increased by the increasing density of the nanocrystals and the whole retention characteristic can be improved. There are much more electrons that can be stored in the double layer than single layer nanocrystal memory device. The double layer CoSi2 nanocrystals have better retention characteristic than the single layer. The good retention characteristic of the double layer device is due to the Coulomb-blockage effects on the top layer nanocrystals from the bottom layer nanocrystals. So, the memory effects of the nonvolatile memory device can be improved by using the double layer nanocrystals. (c) 2007 American Institute of Physics.