Browsing by Author "Lou, JC"

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A novel four-mask-processed poly-Si TFT fabricated using excimer laser crystallization of an edge-thickened alpha-Si active island
(2004-06-01)
Chen, TF
;
Yeh, CF
;
Liu, CY
;
Lou, JC
;
電子工程學系及電子研究所
A novel four-mask-processed polycrystalline silicon thin-film transistor (poly-Si TFT) is fabricated using 50-pulse KrF excimer laser to crystallize an edge-thickened amorphous silicon (a-Si) active island without any shrinkage. This method introduces a temperature gradient in the island to enlarge grains from the edge, especially when the channel width is narrow. The grain boundaries across the width of the channel suppress the leakage current and the drain-induced barrier lowering. Moreover, the proposed poly-Si TFT with a channel length of L = 2 mum and a channel width of W = 1.2 mum possesses a high field-effect mobility of 260 cm(2)/Vs and an on/off current ratio of 2.31 x 10(8).
An interfacial investigation of high-dielectric constant material hafnium oxide on Si substrate
(2005-09-22)
Chen, SC
;
Lou, JC
;
Chien, CH
;
Liu, PT
;
Chang, TC
In this study, the hump in the capacitance-voltage (C-V) curves, variation of leakage current, interfacial layer increase, and electron trapping in non-surface treated hafnium oxide (HfO2) samples were observed and investigated. From the results of the investigation, it was found that both rapid thermal oxidation and NH3 surface treatments improved the C-V curves. In addition, it was observed that samples treated with ammonia exhibited a lower leakage current when compared with the others. From the results of the dielectric, leakage current study, a severe electron trapping effect was exhibited under higher electric field stress. Finally, the conduction mechanism in the HfO2 thin film was dominated by Frenkel-Poole emission in a high electric field. (c) 2005 Elsevier B.V All rights reserved.
Anti-reflection strategies for sub-0.18-mu m dual damascene structure patterning in KrF 248nm lithography
(1999)
Chou, SY
;
Wang, CM
;
Hsia, CC
;
Chen, LJ
;
Hwang, GW
Finding high performance and low cost anti-reflection strategies is a common goal for all photolithographers. This task is getting tough for dual damascene process than the metal-etch process because the oxide thickness variation enhances the thin film interference effect. In this paper, different ARC strategies using organic and inorganic material were examined to compare their CD control performance in sub-0.18 mu m dual damascene structure for KrF 248nm lithography. The organic bottom ARC (BARC) achieves reflectivity control through modulating its thickness. The first and second minimal points in BARC swing curve were chosen as the film thickness to be evaluated. The inorganic ARC, which referred to dielectric ARC (DARC) using PECVD silicon oxynitride (SiOxNy) in this article, was investigated with single layer and double layer structures. The double-layer DARC structure consists of two layers with different extinction coefficient K values. The optimal refractive index (N, K) and thickness of each ARC structure were calculated from some available photolithography simulators. A PECVD process for DARC growth chat provides easily tunable range of refractive index and thickness was established to meet the DW process requirement fr om simulation. The performances of each ARC structure were evaluated on patterning 0.18 mu m trench and 0.20 mu m via in back-end-of-line (BEOL) dual damascene process. It showed that the double-layer DARC provided the most effective CD control ability among these ARC structures. The double-layer DARC should be one of the most potential candidates for sub-0.18 mu m dual damascene process.
Characteristics of the inter-poly Al(2)O(3) dielectrics on NH(3)-nitrided bottom poly-si for next-generation flash memories
(2005-04-01)
Chen, YY
;
Chien, CH
;
Lou, JC
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
The effects of surface NH(3) nitridation of the bottom poly-Si film, and post-deposition annealing (PDA) temperature, on the electrical properties and reliability characteristics of aluminum oxide (Al(2)O(3)) inter-poly capacitors, were evaluated in this study. The polarity-dependent dielectric properties of Al(2)O(3) inter-poly dielectrics (IPDs) were strongly affected by both surface nitridation and the annealing temperature. For positive gate bias, IPDs with NH(3) surface nitridation significantly suppressed the formation of an additional layer with a lower dielectric constant, during the post-annealing process, and obtained a smoother interface, compared to those without nitridation treatment. Furthermore, the presence of a thin Si-N layer made the PDA more effective in eliminating the traps existing in the as-deposited films, and improved dielectric characteristics, under negative polarity. As a result, the smoother interface and smaller electron trapping rate contributed to the drastically reduced leakage current, enhanced breakdown field, and charge to breakdown (Q(bd)) of the Al(2)O(3) inter-poly capacitors with surface NH(3) nitridation. Moreover, the electrical properties of Al(2)O(3) IPD were heavily dependent upon the PDA temperature. The sample exhibited optimal quality in terms of leakage current, electron trapping rate and Qbd when annealed at 900 degrees C. X-ray photoelectron spectroscopy and Auger electron spectroscopy analyses have shown that this occurrence arises from various compositions, under different annealing conditions and excess oxygen, which can act as an electron trapping center, playing an important role in determining IPD electrical properties.
Characteristics of the inter-poly Al2O3 dielectrics on NH3-nitrided bottom poly-si for next-generation flash memories
(2005-04-01)
Chen, YY
;
Chien, CH
;
Lou, JC
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
The effects of surface NH3 nitridation of the bottom poly-Si film, and post-deposition annealing (PDA) temperature, on the electrical properties and reliability characteristics of aluminum oxide (Al2O3) inter-poly capacitors, were evaluated in this study. The polarity-dependent dielectric properties of Al2O3 inter-poly dielectrics (IPDs) were strongly affected by both surface nitridation and the annealing temperature. For positive gate bias, IPDs with NH3 surface nitridation significantly suppressed the formation of an additional layer with a lower dielectric constant, during the post-annealing process, and obtained a smoother interface, compared to those without nitridation treatment. Furthermore, the presence of a thin Si-N layer made the PDA more effective in eliminating the traps existing in the as-deposited films, and improved dielectric characteristics, under negative polarity. As a result, the smoother interface and smaller electron trapping rate contributed to the drastically reduced leakage current, enhanced breakdown field, and charge to breakdown (Q(bd)) of the Al2O3 inter-poly capacitors with surface NH3 nitridation. Moreover, the electrical properties of Al2O3 IPD were heavily dependent upon the PDA temperature. The sample exhibited optimal quality in terms of leakage current, electron trapping rate and Qbd when annealed at 900 degrees C. X-ray photoelectron spectroscopy and Auger electron spectroscopy analyses have shown that this occurrence arises from various compositions, under different annealing conditions and excess oxygen, which can act as an electron trapping center, playing an important role in determining IPD electrical properties.
Damage effect of fluorine implantation on PECVD alpha-SiOC barrier dielectric
(2005-08-01)
Yang, FM
;
Chang, TC
;
Liu, PT
;
Chen, CW
;
Tai, YH
in this work the dielectric properties of plasma enhanced chemical vapor deposited (PECVD) amorphous SiOC (alpha-SiOC) films with various concentrations of oxygen are investigated for the barrier dielectric application. Experimental results show after fluorine (F) ion implanted into alpha-SiOC film, the leakage current in carbide film is increased due to the generation of trap centers. Afterwards, the traps can be effectively repaired after thermal annealing, leading to the decrease of leakage current further. From the extraction of the current-voltage (J-E) characteristics, the conducting mechanism of the leakage current obeys the Poole-Frenkel type behavior for intrinsic, F-implanted and thermally annealed samples. Also, the barrier height of the F-implanted and thermally annealed samples are extracted and exhibits a higher value than that of the intrinsic sample. (c) 2005 Elsevier B.V. All rights reserved.
Effects of channel width and NH3 plasma passivation on electrical characteristics of polysilicon thin-film transistors by pattern-dependent metal-induced lateral crystallization
(2005)
Wu, YC
;
Chang, TC
;
Chou, CW
;
Wu, YC
;
Liu, PT
This work studied the effects of channel width and NH3 plasma passivation on the electrical characteristics of a series of pattern-dependent metal-induced lateral crystallization (PDMILC) polysilicon thin-film transistors (poly-Si TFTs). The performance of PDMILC TFTs improves as each channel width decreasing. Further, PDMILC TFTs with NH3 plasma passivation outperforms without such passivation, resulting from the effective hydrogen passivation of the grain-boundary dangling bonds, and the pile-up of nitrogen at the SiO2/poly-Si interface. In particular, the electrical characteristics of a nanoscale TFT with ten 67 nm wide split channels (M10) are superior to those of other TFTs. The former includes a higher field effect mobility of 84.63 cm(2)/V s, a higher ON/OFF current ratio (> 10(6)), a steeper subthreshold slope (SS) of 230 mV/decade, and an absence of drain-induced barrier lowering (DIBL). These findings originate from the fact that the active channels of the M10 TFT have exhibit the most poly-Si grain enhanced to reduce the grain boundary defects and the best NH3 plasma passivation. Both effects can reduce the number of defects at grain boundaries of poly-Si in active regions for high performances. (c) 2005 The Electrochemical Society. All rights reserved.
Effects of grain boundaries on performance and hot-carrier reliability of excimer-laser annealed polycrystalline silicon thin film transistors
(2004-05-15)
Chen, TF
;
Yeh, CF
;
Lou, JC
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This work examines the effects of grain boundaries on the performance and hot-carrier reliability of excimer-laser-annealed polycrystalline silicon thin film transistors (poly-Si TFTs) before and after NH3 plasma treatment. Self-aligned poly-Si TFTs, whose channel regions include a 150 nm thick laser-crystallized poly-Si layer with small grains and a 100 nm thick layer with large grains, are fabricated. Other TFTs, with large grains throughout their channels, are fabricated nearby for comparison. The trapping of electrons at grain boundaries in the drain junction creates strong local electric fields that boost the leakage current, cause the threshold voltage to decline as the drain bias increases, enhance the kink effect in the output characteristics, and degrade the hot-carrier reliability of devices. When static hot-carrier stress is applied to nonhydrogenated poly-Si TFTs for less than 10(4) s at V-GS=10 V and V-DS=20 V, hot holes are injected into the gate oxide at the same time trap states are created in the drain junction. The screening effect is observed when the same stress is applied to devices that have many grain boundaries in their drain junctions. NH3 plasma treatment prevents the trapping of electrons at grain boundaries. The performance of hydrogenated poly-Si TFTs improves, but the hot-carrier reliability of those TFTs with large grains in their drain junctions degrades. The hydrogenation causes a trade-off between the electrical characteristics and the hot-carrier reliability, and introduces irregular humps in the subthreshold region. (C) 2004 American Institute of Physics.
Evaluating the impact of spherical aberration on sub-0.2-micron contact/via hole patterning
(2001)
Chou, SY
;
Lou, JC
;
Lai, CM
;
Liang, FJ
;
Chen, LJ
Several super resolution techniques, such as phase-shifting mask (PSM) and off-axis illumination (OAI), have been reported to extend the resolution limit and increase the depth-of-focus ( DOF) of optical lithography. However, these techniques provide less immunity to spherical aberration than the conventional approaches like chrome binary mask and low coherent illumination. Best focus position shift is the most well known anomalous phenomenon resulted from spherical aberration. In this paper, the origin of best focus shift is explained in pictorial and analytical forms. The phenomenon is evaluated by observing the exposure-defocus windows of sub-0.2mum hole patterns from an 18 % transmission rim-type attenuated PSM combined with several types of illumination. Under high coherent illumination, severe focus shift was observed in sparse patterns as strong phase-shifting effect is applied. For dense hole patterns,, OAI results in abrupt focus position variation at specific pattern pitch. The experimental results show that spherical aberration would induce best focus shift, distortion of process windows, loss of DOF, and shrink-age of iso/dense process window overlap. Two approaches were proposed to suppress the impact of spherical aberration. One is introducing proper amount of phase bias in attenuated PSM to adjust the wave aberration in the lens. The other more feasible method is using a customized illumination. A synthesized illumination aperture was proposed to compensate the focus shift. Excellent lithographic performance was obtained in the experiment from this method.
Fabricating thin-film transistors on plastic substrates using spin etching and device transfer
(2005)
Wang, SC
;
Yeh, CF
;
Hsu, CT
;
Lou, JC
;
電子工程學系及電子研究所
This work presents a novel method for transferring thin-film transistors (TFTs) from a Si wafer to another flexible plastic substrate. First, high-performance poly-Si TFTs were fabricated on a 1.5 mu m thick SiO2 on a Si wafer and then attached to a flexible plastic substrate by optical adhesive. Next, spin-etching was utilized to remove the backside Si, using SiO2 as a stopping layer. A qualitative model was established to explain the relationship between the chemical flow rate/rotation speed to the etching rate and the uniformity of Si removal. The Si etching rate exceeded 200 mu m/min while the Si to SiO2 selectivity of 250 was maintained given optimized spin-etching parameters. Substrate bonding and Si spin-etching steps caused no degradation or yield loss as compared to the electrical characteristics before transference. Additionally, extrinsic stress only weakly affected the properties of poly-Si resistors and TF`Ts on a flexible plastic substrate. (c) 2005 The Electrochemical Society. [DOI: 10. 1149/1.1860491] All rights reserved.
Fabrication of thin-film transistors on plastic substrates by spin etching and device transfer process
(2004)
Wang, SC
;
Hsu, CT
;
Yeh, CF
;
Lou, JC
;
電子工程學系及電子研究所
This work presents a novel method to transfer thin-film transistors from a Si wafer to another flexible plastic substrate. First, high-performance poly-Si TFTs were fabricated on 1-mum thick SiO2 of a Si wafer and then adhered to a flexible plastic substrate by the optical adhesive. Next, the spin-etching process was utilized to remove the backside Si with SiO2 as a stopping layer. We have established a qualitative model to explain the relation between the chemical flow rate/rotation speed to the etching rate and the uniformity of Si removal. The Si etching rate is higher than 200 mum/min while maintaining Si to SiO2 selectivity of 250 under optimized spin-etching parameters. Compared to that before transference, no degradation or yield loss was found due to substrate bonding and Si spin-etching steps. Additionally, extrinsic stress shows little effect to the properties of poly-Si resistors on the flexible plastic substrate.
Focus latitude enhancement of symmetrical phase mask design for deep submicron contact hole patterning
(2001-11-01)
Chou, SY
;
Lou, JC
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Chen, LJ
;
Shiu, LH
;
Liu, RG
The mechanism of focus latitude enhancement for contact/via hole printing is explained by approximating the axis intensity distribution of an image as a series of cosine functions to characterize the interference between each pair of diffraction beams. It is found that a phase-shifting mask (PSM) with symmetrical assist features improves the depth of focus (DOF) by introducing destructive interference to counterbalance the intensity fluctuation from constructive interference as defocus. A simple formula was derived to represent the capability of focus latitude enlargement. It shows that the extent of enhancement depends on the exposure wavelength and numerical aperture of a projection lens only. Increasing the degree of partial coherence degrades the focal range enlargement because a larger illumination angle elongates the destructive interference pattern in the optical-axis direction to weaken its ability for intensity compensation. On the other hand, the lack of constructive interference in dense hole imaging fails the mask pattern transfer, which limits the application of the phase-shifting method to pattern pitch greater than root2lambda/NA. A tiny amount of spherical aberration results in prominent asymmetrical defocus behavior because the wave deformation in the projection lens shifts the distribution of constructive and destructive interference patterns to opposite defocus directions. The printing characteristics of 0.17 mum contact using an 18% transmission, rim-type attenuated phase-shifting mask are investigated to corroborate our analysis of defocus behavior. The dependence of depth of focus on pattern duty is stressed to elucidate the difference in mechanisms of focus latitude improvements for a sparse hole and periodic dense hole. (C) 2001 American Vacuum Society.
Gate oxynitride grown in N2O and annealed in no using rapid thermal processing
(1995)
Sun, SC
;
Chen, CH
;
Lou, JC
;
Yen, LW
;
Lin, CJ
High quality Al2O3IPD with NH3 surface nitridation
(2003-08-01)
Chen, YY
;
Chien, CH
;
Lou, JC
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
In this letter, the effect of surface NH3 nitridation on the electrical properties and reliability characteristics of aluminum oxide (Al2O3) interpoly capacitors is studied. With NH3 surface nitridation, the formation of an additional layer with lower dielectric constant during post-annealing process can be significantly suppressed, compared to that without nitridation treatment. Furthermore, the presence of a thin Si-N layer can make post-deposition annealing more effective in eliminating traps existing in the as-deposited films. As a result, a smoother interface and smaller electron trapping rate can contribute to the drastically reduced leakage current, enhanced breakdown field and charge to breakdown (Q(bd)) of Al2O3 interpoly capacitors with surface NH3 nitridation.
Impact of air filter material on metal oxide semiconductor (MOS) device characteristics in HF vapor environment
(2004-05-15)
Hsiao, CW
;
Lou, JC
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Yeh, CF
;
Hsieh, CM
;
Lin, SJ
Airborne molecular contamination (AMC) is becoming increasingly important as devices are scaled down to the nanometer generation. Optimum ultra low penetration air (ULPA) filter technology can eliminate AMC. In a cleanroom, however, the acid vapor generated from the cleaning process may degrade the ULPA filter, releasing AMC to the air and the surface of wafers, degrading the electrical characteristics of devices. This work proposes the new PTFE ULPA filter, which is resistant to acid vapor corrosion, to solve this problem. Experimental results demonstrate that the PTFE ULPA filter can effectively eliminate the AMC and provide a very clean cleanroom environment.
Investigation of grain boundary control in the drain junction on laser-crystalized poly-Si thin film transistors
(2003-07-01)
Chen, TF
;
Yeh, CF
;
Lou, JC
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This letter investigates the influences of grain boundaries in the drain junction on the performance and reliability of laser-crystalized poly-Si thin film transistors (TFTs). A unique test structure where the channel. region includes 150-nm-thick laser-crystalized poly-Si with, small grain sizes and a 100-nm-thick one with large grain sizes is fabricated. Different behaviors in the electrical characteristics and reliability of a single TFT are observed under measurements of the forward mode and then under first measurements of the reverse mode. This is due to the different number of, grain boundaries in the drain junction. Grain boundaries in the drain junction were found to cause reduced ON/OFF current ratio, variations in threshold voltage With drain bias, significantly, increased kink effect in the output characteristics, and poor hot-carrier stress endurance.
Mobility enhancement of polycrystalline-Si thin-film transistors using nanowire channels by pattern-dependent metal-induced lateral crystallization
(2005-10-03)
Wu, YC
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Chang, TC
;
Liu, PT
;
Wu, YC
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Chou, CW
This work presents a method for enhancing the mobility of polycrystalline-Si (poly-Si) thin-film transistors (TFTs) by pattern-dependent metal-induced-lateral-crystallization (PDMILC) using nanowire channels. Experimental results indicate that the field-effect mobility of PDMILC TFT was enhanced as the channel width decreased, because the lateral length of the poly-Si grains increased. The PDMILC poly-Si TFT with ten nanowire channels (M10) had the greatest field-effect mobility, 109.34 cm(2)/V s and the lowest subthreshold swing, 0.23 V/dec, at a gate length of 2 mu m. The field-effect mobility also increased as the gate length in the M10 PDMILC poly-Si TFT device declined, because the number of poly-Si grain-boundary defects was reduced. (C) 2005 American Institute of Physics.
MOS characteristics of N2O-grown and NO-annealed oxynitrides
(1995)
Sun, SC
;
Chen, CH
;
Lou, JC
;
奈米中心
;
Nano Facility Center
Process improvement and reliability characteristics of spin-on poly-3-hexylthiophene thin-film transistor
(2005)
Wang, SC
;
Lou, JC
;
Liou, BL
;
Lin, RX
;
Yeh, CF
Poly-3-hexylthiophene (P3HT) based thin-film transistors were fabricated. Various spin-coating conditions including spin speeds, curing temperatures, solvents, and weight percentages of P3HT have been examined. It was found that the P3HT of 0.3 wt % dissolved in chloroform contributes to the lowest surface roughness and the highest ON/OFF current ratio over four orders of magnitude. Besides, the anomalous gate leakage current was eliminated successfully by growing a thick field oxide layer in the source/drain regions. Through O-2, N-2, H2O, or high-vacuum treatments, it was confirmed that the threshold voltage and mobility of organic devices degrades rapidly when the P3HT-based organic thin-film transistors were exposed to the O-2 atmosphere within 8 h. Moreover, the threshold voltage increases under a positive gate bias stress while the V-th decreases after a negative gate bias stress. The mechanism was attributed to the polarization effect of P3HT film. (C) 2004 The Electrochemical Society.