Browsing by Author "Lu, C. Y."

Now showing 1 - 16 of 16

A Comparative Study of NBTI and RTN Amplitude Distributions in High-kappa Gate Dielectric pMOSFETs
(2012-02-01)
Chiu, J. P.
;
Chung, Y. T.
;
Wang, Tahui
;
Chen, Min-Cheng
;
Lu, C. Y.
Random telegraph noise (RTN) and negative bias temperature (NBT) stress-induced threshold voltage (V-t) fluctuations in high-kappa gate dielectric and metal-gate pMOSFETs are investigated. We measured RTN amplitude distributions before and after NBT stress. RTN in poststressed devices exhibits a broader amplitude distribution than the prestress one. In addition, we trace a single trapped charge-induced Delta V-t in NBT stress and find that the average Delta V-t is significantly larger than a Delta V(t)caused by RTN. A 3-D atomistic simulation is performed to compare a single-charge-induced Delta V-t by RTN and NBTI. In our simulation, the probability distribution of a NBT trapped charge in the channel is calculated from the reaction-diffusion model. Our simulation confirms that the NBT-induced Delta V-t indeed has a larger distribution tail than RTN due to a current-path percolation effect.
A highly reliable self-aligned graded oxide WOx resistance memory: Conduction mechanisms and reliability
(2007-01-01)
Ho, ChiaHua
;
Lai, E. K.
;
Lee, M. D.
;
Pan, C. L.
;
Yao, Y. D.
WOx formed by plasmas oxidation shows promising multibit/cell resistance memory characteristics [1]. The simple memory is completely self-aligned, requiring no additional masks and has a small 6F(2) cell size. In this work we introduce a graded oxide device that is highly reliable (250 degrees C baking for > 2,000 hrs). The conduction mechanism and factors affecting the memory reliability are examined extensively.
Cell Endurance Prediction from a Large-area SONOS Capacitor
(2009)
Lee, C. H.
;
Tu, W. H.
;
Gu, S. H.
;
Wu, C. W.
;
Lin, S. W.
Endurance considerations induced by the degadation of top and bottom oxides are proposed for a SONOS memory. First, a correlation is found between the widespread C-V curves induced by interface generation and cycling numbers (cyc. #). Unlike V-FB (accumulation region), V-T (inversion region) shows a much severe shift. Inter-face state (N-it) is identified as a key factor even when a 2nm bottom oxide is used. Moreover, charge to breakdown (Q(BD)) for an ONO capacitor under positive and negative constant current stress (CCS) is investigated. Our study reveals that QBD of such stacks strongly depends on the top oxide thickness. A field enhancement induced by charges in a trapping nitride layer is the root cause. Based on Weibull statistics, the risk of dielectric breakdown for both blocking layers is then evaluated.
Defect density reduction of the Al(2)O(3)/GaAs(001) interface by using H(2)S molecular beam passivation
(2011-10-01)
Merckling, C.
;
Chang, Y. C.
;
Lu, C. Y.
;
Penaud, J.
;
Brammertz, G.
The integration of higher carrier mobility materials to increase drive current capability in the next CMOS generations is required for device scaling. But a fundamental issue regarding the introduction of high-mobility III-V in CMOS is the electrical passivation of the interface with the high-kappa gate dielectric. In this work, we show that in situ H(2)S surface treatment on GaAs(001) leads to a stable and reorganized oxide/III-V interface. The exposition of the GaAs surface is monitored in situ by RHEED and the interface is characterized by XPS analyses. Finally, MOS capacitors are fabricated to extract interface state density over the band gap. These results highlight a promising re-interest in chalcogenide passivation of III-V surfaces for CMOS applications. (C) 2011 Elsevier B.V. All rights reserved.
Defect density reduction of the Al2O3/GaAs(001) interface by using H2S molecular beam passivation
(2011-10-01)
Merckling, C.
;
Chang, Y. C.
;
Lu, C. Y.
;
Penaud, J.
;
Brammertz, G.
The integration of higher carrier mobility materials to increase drive current capability in the next CMOS generations is required for device scaling. But a fundamental issue regarding the introduction of high-mobility III-V in CMOS is the electrical passivation of the interface with the high-kappa gate dielectric. In this work, we show that in situ H2S surface treatment on GaAs(001) leads to a stable and reorganized oxide/III-V interface. The exposition of the GaAs surface is monitored in situ by RHEED and the interface is characterized by XPS analyses. Finally, MOS capacitors are fabricated to extract interface state density over the band gap. These results highlight a promising re-interest in chalcogenide passivation of III-V surfaces for CMOS applications. (C) 2011 Elsevier B.V. All rights reserved.
Development of new features of ant colony optimization for flowshop scheduling
(2008-04-01)
Lin, B. M. T.
;
Lu, C. Y.
;
Shyu, S. J.
;
Tsai, C. Y.
;
資訊管理與財務金融系註：原資管所+財金所
Ant colony optimization (ACO) is a meta-heuristic based on the indirect communication of a colony of artificial ants mediated by pheromone trails with the collaboration and knowledge-sharing mechanism during their food-seeking process. In this study, we introduce two new features that are inspired from real ant behavior to develop a new ACO algorithm to produce better solutions. The proposed ACO algorithm is applied to two NP-hard flowshop scheduling problems. The first problem is to minimize the total completion time and the second is to minimize a combination of makespan and total completion time. Numerical results indicate that the proposed new features of ACO are very effective and the synergy of combining all the new features for the proposed ACO algorithm can solve the two problems to a certain scale by producing schedules of better quality. (C) 2007 Elsevier B.V. All rights reserved.
Device Instability of ReRAM and a Novel Reference Cell Design for Wide Temperature Range Operation
(2017-09-01)
Lin, Y. H.
;
Lin, Y. Y.
;
Lee, F. M.
;
Ho, Y. H.
;
Hsu, K. C.
This letter addresses two difficult challenges for transition metal oxide resistive random access memories (ReRAMs)-sensitivity to operation temperature and random fluctuation of resistance value. A careful study of a WOx ReRAM array reveals that these devices are unstable and their read currents fluctuate with time due to random telegraph noise and structure relaxation. Consequently, even after careful programming, the current distribution can broaden with time and tail bit population grows. Furthermore, ReRAM state is sensitive to temperature and a reference cell made of the same device material must be used. Thus, although the broadening of read current distribution may be tolerated by creating a larger RESET/SET memory window, the current fluctuation still makes it impossible to predict the output of the reference cell, leading to array malfunction. This letter investigates the current (resistance) instability in detail and proposes a reference array with a novel trimming method that can stabilize the reference current level. The proposed reference array has very good dc stress reliability as well as wide-range temperature tracking performance from -40 degrees C to 85 degrees C.
Dynamic NBTI characteristics of PMOSFETs with PE-SiN capping
(2007-06-01)
Lu, C. Y.
;
Lin, H. C.
;
Lee, Y. J.
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Negative-bias-temperature instability (NBTI) characteristics of strained p-channel metal-oxide-semiconductor field-effect transistors (PMOSFETs) under dynamic and AC stressing were investigated in this work. The compressive strain in the channel was deliberately induced by a plasma-enhanced chemical vapor deposition (PECVD) silicon nitride (SiN) capping layer in this study. It was found that the capping would degrade the NBTI characteristics, although the degradation is relieved when the stress frequency increases. The aggravated NBTI behaviors are ascribed to the higher amount of hydrogen incorporation during SiN deposition. (c) 2006 Published by Elsevier Ltd.
Electrical Characterization of Al(2)O(3)/n-InAs Metal-Oxide-Semiconductor Capacitors With Various Surface Treatments
(2011-06-01)
Trinh, H. D.
;
Brammertz, G.
;
Chang, E. Y.
;
Kuo, C. I.
;
Lu, C. Y.
Ex situ sulfide and HCl wet chemical treatments in conjunction with in situ trimethyl aluminum (TMA) pretreatment were performed before the deposition of Al(2)O(3) on n-InAs surfaces. X-ray photoelectron spectroscopy analyses show a significant reduction of InAs native oxides after different treatments. The capacitance-voltage C-V characterization of Al(2)O(3)/n-InAs structures shows that the frequency dispersion in the accumulation regime is small (< 0.75%/dec) and does not seem to be significantly affected by the different surface treatments, whereas the latter improves depletion and inversion behaviors of the n-channel metal-oxide-semiconductor capacitors. The interface trap density profiles extracted from the simulation mainly show donorlike interface states inside the InAs band gap and in the lower part of the conduction band. The donorlike traps inside the InAs band gap and in the lower part of the conduction band were significantly reduced by using wet-chemical-plus-TMA treatments, in agreement with C-V characteristics.
Electrical Characterization of Al2O3/n-InAs Metal-Oxide-Semiconductor Capacitors With Various Surface Treatments
(2011-06-01)
Trinh, H. D.
;
Brammertz, G.
;
Chang, E. Y.
;
Kuo, C. I.
;
Lu, C. Y.
Ex situ sulfide and HCl wet chemical treatments in conjunction with in situ trimethyl aluminum (TMA) pretreatment were performed before the deposition of Al2O3 on n-InAs surfaces. X-ray photoelectron spectroscopy analyses show a significant reduction of InAs native oxides after different treatments. The capacitance-voltage C-V characterization of Al2O3/n-InAs structures shows that the frequency dispersion in the accumulation regime is small (< 0.75%/dec) and does not seem to be significantly affected by the different surface treatments, whereas the latter improves depletion and inversion behaviors of the n-channel metal-oxide-semiconductor capacitors. The interface trap density profiles extracted from the simulation mainly show donorlike interface states inside the InAs band gap and in the lower part of the conduction band. The donorlike traps inside the InAs band gap and in the lower part of the conduction band were significantly reduced by using wet-chemical-plus-TMA treatments, in agreement with C-V characteristics.
Experimental and modeling on atomic layer deposition Al2O3/n-InAs metal-oxide-semiconductor capacitors with various surface treatments
(2011-01-01)
Trinh, H. D.
;
Chang, E. Y.
;
Brammertz, G.
;
Lu, C. Y.
;
Nguyen, H. Q.
Ex-situ sulfide and HCl wet chemical treatments in conjunction with in-situ trimethyl aluminum (TMA) pretreatment were performed before the deposition of Al2O3 on n-InAs surfaces. X-ray photoelectron spectroscopy analyses show a significant reduction of InAs native oxides after different treatments. Capacitance-voltage (C-V) characterization of Al2O3/n-InAs structures shows that the frequency dispersion in accumulation regime is small (<0.75% per decade) and does not seem to be affected significantly by the different surface treatments, whereas the latter improves depletion and inversion behaviors of the nMOS capacitors. The interface trap density profiles extracted from simulation show mainly donor-like interface states inside the InAs bandgap and in the lower part of the conduction band. The donor-like traps inside the InAs bandgap and in the lower part of the conduction band were significantly reduced by using wet chemical plus TMA treatments, in agreement with C-V characteristics.
Experimental and modeling on atomic layer deposition Al2O3/n-InAs metal-oxide-semiconductor capacitors with various surface treatments
(2011-01-01)
Trinh, H. D.
;
Chang, E. Y.
;
Brammertz, G.
;
Lu, C. Y.
;
Nguyen, H. Q.
Ex-situ sulfide and HCl wet chemical treatments in conjunction with in-situ trimethyl aluminum (TMA) pretreatment were performed before the deposition of Al2O3 on n-InAs surfaces. X-ray photoelectron spectroscopy analyses show a significant reduction of InAs native oxides after different treatments. Capacitance-voltage (C-V) characterization of Al2O3/n-InAs structures shows that the frequency dispersion in accumulation regime is small (<0.75% per decade) and does not seem to be affected significantly by the different surface treatments, whereas the latter improves depletion and inversion behaviors of the nMOS capacitors. The interface trap density profiles extracted from simulation show mainly donor-like interface states inside the InAs bandgap and in the lower part of the conduction band. The donor-like traps inside the InAs bandgap and in the lower part of the conduction band were significantly reduced by using wet chemical plus TMA treatments, in agreement with C-V characteristics.
H(2)S molecular beam passivation of Ge(001)
(2011-04-01)
Merckling, C.
;
Chang, Y. C.
;
Lu, C. Y.
;
Penaud, J.
;
El-Kazzi, M.
A fundamental issue regarding the introduction of high-mobility Ge channels in CMOS circuits is the electrical passivation of the interface with the high-k gate dielectric. In this paper, we investigate the passivation of p-Ge(0 0 1) using molecular H(2)S. The modification of the semiconductor surface is monitored in situ by RHEED and the interface is characterized by XPS analyses. MOS capacitors are fabricated to extract interface state density, and finally we demonstrate the efficiency of the passivation scheme using a combination with an ultra thin Al interlayer. (C) 2010 Elsevier B.V. All rights reserved.
H2S molecular beam passivation of Ge(001)
(2011-04-01)
Merckling, C.
;
Chang, Y. C.
;
Lu, C. Y.
;
Penaud, J.
;
El-Kazzi, M.
A fundamental issue regarding the introduction of high-mobility Ge channels in CMOS circuits is the electrical passivation of the interface with the high-k gate dielectric. In this paper, we investigate the passivation of p-Ge(0 0 1) using molecular H2S. The modification of the semiconductor surface is monitored in situ by RHEED and the interface is characterized by XPS analyses. MOS capacitors are fabricated to extract interface state density, and finally we demonstrate the efficiency of the passivation scheme using a combination with an ultra thin Al interlayer. (C) 2010 Elsevier B.V. All rights reserved.
Influence of the device geometry on the Schottky gate characteristics of AlGaN/GaN HEMTs
(2010-07-01)
Lu, C. Y.
;
Bahat-Treidel, E.
;
Hilt, O.
;
Lossy, R.
;
Chaturvedi, N.
In this work, we investigate the relevance of device geometry to the Schottky gate characteristics of AlGaN/GaN high electron mobility transistors. Changes of three-terminal gate turn-on voltage and gate leakage current on the gate-drain spacing, source-gate spacing and recess depth have been observed. Further examinations comparing device simulations and measurements suggest that gate turn-on voltage is influenced by the distribution of electric potential under the gate region which is related to the geometry. By proper design of the device, high gate turn-on voltage can be obtained for both depletion-mode and recessed enhancement-mode devices.
Overall Operation Considerations for a SONOS-based Memory
(2009)
Lee, C. H.
;
Tu, W. H.
;
Chong, L. H.
;
Gu, S. H.
;
Chen, K. F.
Erase characteristics of a SONOS-based structure are emulated not only for n(+)-poly and p(+)-poly gates but also for TaN-gate+Al2O3 combination. By incorporating our previous studies, performances including program, erase, and read disturb can be reviewed for both SONOS and TANOS devices. Unsurprisingly, it is hard to satisfy all requirements by using a SONOS device. In a TANOS device, an optimal bottom oxide thickness can be specified with the consideration of the three factors simultaneously. Moreover, it is found that conventional extrapolation methodology is inadequate to predict the lifetime of a TANOS device and tends to under-estimate the tolerable read bias.