Browsing by Author "Lu, Chao-Hung"

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An effective decap insertion method considering power supply noise during floorplanning
(2008-01-01)
Lu, Chao-Hung
;
Chen, Hung-Ming
;
Liu, Chien-Nan Jimmy
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
As VLSI technology enters the nanometer era, the supply voltage is continually dropped. This condition helps to reduce the power dissipation, but make the power integrity problem become worse. Employing decoupling capacitances (decap) at floorplan stage has been a common approach to alleviate the supply noise problem. However, the decap budget is often overly estimated in previous researches. Besides the decap budget computation, the available floorplan space does not fully used in previous works. In one floorplan, it usually has many available spaces except the empty space that could be used to insert the decap without increasing the floorplan area. Therefore, our goal in this work is to develop a better model to calculate the required decap to solve the power supply noise problem of area-array based designs and to increase he usage of the available space in the floorplan to reduce the area overhead caused by decap insertion. The experimental results are encouraging. Compared with other approaches, our algorithm can reduce 52.6% decap budget on the MCNC benchmarks but still keep the power supply noise in the given constraint. The final floorplan areas with decap are also less than the numbers reported in previous papers.
Design Planning with 3D-Via Optimization in Alternative Stacking Integrated Circuits
(2011-01-01)
Lu, Chao-Hung
;
Chen, Hung-Ming
;
Liu, Chien-Nan Jimmy
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Billions of transistors are placed in one single chip (SoC) with advanced manufacturing technology. Further development is obstructed by the ability to the manufacture of SoC and the signal integrity. Stacking IC is an alternative choice when we design a high-performance high-density chip. Design flow (especially physical design) is facing different issues when compared with 2D IC design. The location of the I/Os seriously affect the number of 3D-Vias and their total area in the stacking IC. This paper proposes a Stacking IC architecture and the corresponding design flow to solve the I/O and 3D-Via problems. In this flow, we have developed a system partition approach to minimize the number of 3D-Vias and balance the I/O number of each tier, and modified one traditional floorplan method to optimize the I/O and module locations. The experimental results are encouraging in the GSRC benchmarks. Compared with greedy and intuitive methods, our framework reduces the number of 3D-Vias by 30.02% on the average and can balance the I/O count of each tier. The dead space of the final floorplan is reduced by 14.13%.
Effective Decap Insertion in Area-Array SoC Floorplan Design
(2008-09-01)
Lu, Chao-Hung
;
Chen, Hung-Ming
;
Liu, Chien-Nan Jimmy
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
As VLSI technology enters the nanometer era, supply voltages continue to drop due to the reduction of power dissipation, but it makes power integrity problems even worse. Employing decoupling capacitances (decaps) in floorplan stage is a common approach to alleviating supply noise problems. Previous researches overestimate the decap budget and do not fully utilize the empty space of the floorplan. A floorplan usually has a lot of available space that can be used to insert the decap without increasing the floorplan area. Therefore, the goal of this work is to develop a better model to calculate the required decap to solve the power supply noise problem in area-array based designs, and increase the usage of available space in the floorplan to reduce the area overhead caused by decap insertion. The experimental results of this work are encouraging. Compared with previous approaches, our methodology reduces 38% of the decap budget in average for MCNC benchmarks but can still meet the power supply noise requirements. The final floorplan areas with decap are also smaller than the numbers reported in previous works.
On increasing signal integrity with minimal decap insertion in area-array SoC floorplan design
(2007)
Lu, Chao-Hung
;
Chen, Hung-Ming
;
Liu, Chien-Nan Jimmy
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
With technology further scaling into deep submicron era, power supply noise become an important problem. Power supply noise problem is getting worse due to serious IR-drop and simultaneous switching noise, and decoupling capacitance (decap) insertion is commonly applied to alleviate the noise. There exist some approaches to addressing this issue, but they suffer either from over-design problem or late decap insertion during design stage. In this paper, we propose a methodology to insert decap in a more efficient and effective way during early design stage in area-array designs. The experimental results are encouraging. Compared with other approaches in [15] and [12], we have inserted enough decap to meet supply noise constraint while others employ more area.
Package Routability- and IR-Drop-Aware Finger/Pad Assignment in Chip-Package Co-Design
(2009)
Lu, Chao-Hung
;
Chen, Hung-Ming
;
Liu, Chien-Nan Jimmy
;
Shih, Wen-Yu
;
電子工程學系及電子研究所
Due to increasing complexity of design interactions between the chip, package and PCB, it is essential to consider them at the same time. Specifically the finger/pad locations affect the performance of the chip and the package significantly. In this paper, we have. developed techniques in chip-package codesign to decide the locations of fingers/pads for package routability and signal integrity concerns in chip core design. Our finger/pad assignment is a two-step method: first we optimize the wire congestion problem in package routing, and then we try to minimize the IR-drop violation with finger/pad solution refinement The experimental results are encouraging. Compared with the randomly optimized methods, our approaches reduce in average 42% and 68% of the maximum density in package and 10.61% of IR-drop for test circuits.
Package routability- and IR-drop-aware finger/pad planning for single chip and stacking IC designs
(2013-06-01)
Lu, Chao-Hung
;
Chen, Hung-Ming
;
Liu, Chien-Nan Jimmy
;
Shih, Wen-Yu
;
電子工程學系及電子研究所
Due to the increasing complexity of the design interactions between the chip and package, it is necessary to consider them at the same time. In order to simultaneously handle chip and package performances, co-design of chip and package is a widely adopted solution, particularly because the finger/pad locations significantly affect IR-drop of the core and the package routing. In this paper, we develop chip-package co-design techniques to determine the locations of the fingers/pads for package routability and signal integrity concerns in IC designs, this method can be used in the 2-D and stacking IC design. Our finger/pad assignment is a two-step method: we first solve the wire congestion problem in package routing, and then try to minimize the IR-drop violation and the length of the bonding wires under a compact IR-drop model. The experimental results are encouraging. Compared with the randomly optimized method, on average, our approaches reduce the maximum package density by 42% and 68% for both technologies, IR-drop by 10.61% and 4.58%; and the bonding wires is reduced by 15.66% if we use stacking chips. (c) 2012 Elsevier B.V. All rights reserved.
Using power gating techniques in area-array SoC floorplan design
(2007-01-01)
Yeh, Chi-Yi
;
Chen, Hung-Ming
;
Huang, Li-Da
;
Wei, Wei-Ting
;
Lu, Chao-Hung
Low power demand drives the development of lower power design architectures, among which power gating is one of the state-of-the-art techniques to achieve low power. NITCMOS (or sleep transistor) is applied when some of the blocks can be switched off without leakage power dissipation. This technique is widely used in circuit level design, but hardly used in higher level design stage. Due to early planning in power delivery for area-array design style, it is necessary to consider the power gating techniques in early SoC physical design stage. This paper presents a framework to insert coarse grain MTCMOS in SoC floorplanning stage, saving mainly leakage power. This work decides which modules have chance to save power by sleep transistors insertion, and reserves enough area for them during floorplarming. The results show that our approach works well and can obtain lower power floorplans with supply noise aware sleep transistor insertion in area-array architecture.