Browsing by Author "Lu, Chi-Pei"

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Bias-Dependent Source Injection Resistance of Modified Schottky Barrier MOSFET
(2008)
Tsui, Bing-Yue
;
Lu, Chi-Pei
;
Liu, Hsiao-Han
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Modified Schottky Barrier MOSFET with low resistance metal source/drain and good short channel effect immunity is one of the promising nano-scale device structures. In this work, a modified external load resistance method was proposed to extract the bias dependent source injection resistance of the MSB multi-gate MOSFET. The injection resistance is exponentially proportional to (V(GS)-V(th)-0.5V(DS)) and would be close to the source/drain resistance of conventional MOSFET at high gate bias.
Current transport mechanisms of Schottky barrier and modified schottky barrier MOSFETs
(2007)
Tsui, Bing-Yue
;
Lu, Chi-Pei
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Current transport mechanisms of Schottky barrier (SB) and Modified Schottky barrier (MSB) MOSFETs are investigated by measuring the temperature effect on current-voltage characteristics. For SB MOSFETs, current transport could be dominated by thermionic emission or tunneling mechanism depends on the Schottky barrier height and the gate voltage. The current transport of the MSB MOSFETs changes from tunneling mechanism to drift-diffusion mechanism as the gate voltage increases. The changing point is a good indicator to evaluate the efficiency of the MSB junction. Since the current transport mechanism depends on bias condition, the extraction of mobility should be treated carefully, especially at low gate voltage.
Method for extracting gate-voltage-dependent source injection resistance of modified Schottky barrier (MSB) MOSFETs
(2008-09-01)
Tsui, Bing-Yue
;
Lu, Chi-Pei
;
Liu, Hsiao-Han
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
The modified Schottky barrier (MSB) MOSFET with low-resistance metal source/drain and good short-channel effect immunity is one of the promising nanoscale device structures. In this letter, a modified external load resistance method was proposed to extract the bias-dependent source injection resistance of the MSB MOSFET for the first time. The effect of the thermal budget of the MSB process on the source injection resistance is reported. The injection resistance is exponentially proportional to (V-GS-V-th-0.5V(DS)) and would, be close to the source/drain resistance of conventional MOSFETs at high gate bias. This work provides a good method to directly evaluate the efficiency of the MSB junction.
Nanoscale Multigate TiN Metal Nanocrystal Memory Using High-k Blocking Dielectric and High-Work-Function Gate Electrode Integrated on Silcon-on-Insulator Substrate
(2009-04-01)
Lu, Chi-Pei
;
Luo, Cheng-Kei
;
Tsui, Bing-Yue
;
Lin, Cha-Hsin
;
Tzeng, Pei-Jer
In this study, a charge-trapping-layer-engineered nanoscale n-channel trigate TiN nanocrystal nonvolatile memory was successfully fabricated on silicon-on-insulator (SOI) wafer. An Al(2)O(3) high-k blocking dielectric layer and a P(+) polycrystalline silicon gate electrode were used to obtain low operation voltage and suppress the back-side injection effect, respectively. TiN nanocrystals were formed by annealing TiN/Al(2)O(3) nanolaminates deposited by an atomic layer deposition system. The memory characteristics of various samples with different TiN wetting layer thicknesses, post-deposition annealing times, and blocking oxide thicknesses were also investigated. The sample with a thicker wetting layer exhibited a much larger memory window than other samples owing to its larger nanocrystal size. Good retention with a mere 12% charge loss for up to 10 years and high endurance were also obtained. Furthermore, gate disturbance and read disturbance were measured with very small charge migrations after a 10(3) s stressing bias. (C) 2009 The Japan Society of Applied Physics
Trigate TiN Nanocrystal Memory with High-k Blocking Dielectric and High Work Function Gate Electrode
(2009)
Lu, Chi-Pei
;
Tsui, Bing-Yue
;
Luo, Cheng-Kei
;
Lin, Cha-Hsin
;
Tzeng, Pei-Jer
In this work, high-performance TiN metal nanocrystal nonvolatile memories using a p(+) poly-Si gate and a Al(2)O(3) blocking dielectric layer with trigate structure are fabricated on silicon-on-insulator substrate. Devices with moderate transistor performance and superior memory properties are demonstrated. A memory window as high as 5 V is achieved after Program/Ease (P/E) operation at +/- 10 V for 0.1 s, with only 18 and 33% charge loss at room temperature and at 85 degrees C after 10 years storage. Only +0.5 V window shift and almost no window narrowing after 10(5) P/E operations can be obtained. Furthermore, a device with larger nanocrystals has better P/E characteristics and superior retention performance. (C) 2008 The Electrochemical Society. [DOI: 10.1149/1.3054304] All rights reserved.