Browsing by Author "Lu, Chien-Yu"

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A 0.325 V, 600-kHz, 40-nm 72-kb 9T Subthreshold SRAM with Aligned Boosted Write Wordline and Negative Write Bitline Write-Assist
(2015-05-01)
Lu, Chien-Yu
;
Chuang, Ching-Te
;
Jou, Shyh-Jye
;
Tu, Ming-Hsien
;
Wu, Ya-Ping
This brief presents a two-port disturb-free 9T subthreshold static random access memory (SRAM) cell with independent single-ended read bitline and write bitline (WBL) and cross-point data-aware write structure to facilitate robust subthreshold operation and bit-interleaving architecture for enhanced soft error immunity. The design employs a variation-tolerant line-up write-assist scheme where the timing of area-efficient boosted write wordline and negative WBL are aligned and triggered/initiated by the same low-going global WBL to maximize the write-ability enhancement. A 72-kb test chip is implemented in United Microelectronics Corp. 40-nm low-power (40LP) CMOS. Full functionality is achieved for V-DD ranging from 1.5 to 0.32 V without redundancy. The measured maximum operation frequency is 260 MHz (450 kHz) at 1.1 V (0.32 V) and 25 degrees C. At 0.325 V and 25 degrees C, the chip operates at 600 kHz with 5.78 mu W total power and 4.69 mu W leakage power, offering 2x frequency improvement compared with 300 kHz of our previous 72-kb 9T subthreshold SRAM design in the same 40LP technology. The energy efficiency (power/frequency/IO) at 0.325 V and 25 degrees C is 0.267 pJ/bit, a 23.7% improvement over the 0.350 pJ/bit of our previous design.
A 0.33-V, 500-kHz, 3.94-mu W 40-nm 72-Kb 9T Subthreshold SRAM With Ripple Bit-Line Structure and Negative Bit-Line Write-Assist
(2012-12-01)
Lu, Chien-Yu
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Tu, Ming-Hsien
;
Yang, Hao-I
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Wu, Ya-Ping
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Huang, Huan-Shun
This paper presents an ultra-low-power 72-Kb 9T static random-access memory (SRAM) with a ripple bit-line (RPBL) structure and negative bit-line (NBL) write-assist. The RPBL scheme provides over 40% read access performance improvement for VDD below 0.4 V compared with the conventional hierarchical bit-line structure. A variation-tolerant ripple-initiated NBL write-assist scheme with the transient negative pulse coupled only into the single selected local bit-line segment is employed to enhance the NBL, boosting efficiency and reducing power consumption. The 331 x 385 mu m(2) 72-Kb SRAM macro has been fabricated in UMC 40-nm low-power CMOS technology and was tested with full suites of SRAM compiler qualification patterns. Error-free full functionality without redundancy is achieved from 1.5 V down to 0.33 V. The measured maximum operation frequency is 220 MHz (500 kHz) at 1.1 V (0.33 V) and 25 degrees C. The measured total power consumption is 3.94 mu W at 0.33 V, 500 kHz, and 25 degrees C.
A 0.35 V, 375 kHz, 5.43 mu W, 40 nm, 128 kb, symmetrical 10T subthreshold SRAM with tri-state bit-line
(2016-05)
Wu, Shang-Lin
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Lu, Chien-Yu
;
Tu, Ming-Hsien
;
Huang, Huan-Shun
;
Lee, Kuen-Di
This paper presents a disturb-free 10T subthreshold SRAM cell with fully-symmetrical structure and tristate pre-charge free bit-line (BL). The disturb-free feature facilitates bit-interleaving architecture that can reduce multiple-bit errors in a single word and enhance soft error immunity by employing error checking and correction (ECC) techniques. The fully-symmetrical cell structure provides balanced margin and performance in advanced strained-silicon and/or FinFET technologies where PMOS strength approaches that of NMOS. The tri-state BL is left floating in standby state to minimize switching activity for energy efficiency. The scheme eliminates the need of BL keeper, provides balanced two-transistor stack read for better read performance, and eases the design and migration. The proposed 10T SRAM cell is demonstrated by 128 kb SRAM macro implemented in 40 nm low-power (40LP) CMOS technology. Measured read and write functionality is demonstrated with V-DD down to 0.35 V (similar to 100 mV lower than the threshold voltage). Data is held down to 0.325 V with 2.53 mu W standby power. The measured maximum operation frequency is 375 kHz with total power consumption 5.43 mu W at 0.35 V. (C) 2016 Elsevier Ltd. All rights reserved.
A Disturb-Free Subthreshold 9T SRAM Cell With Improved Performance and Variation Tolerance
(2013-01-01)
Lu, Chien-Yu
;
Chuang, Ching-Te
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This paper presents a novel subthreshold 9T SRAM cell with row-based Word-Line (WL) and column-based data-aware Write Word-Lines (WWLs). The decoupled Read port and cross-point Write structure provide a disturb-free cell and facilitate bit-interleaving architecture to improve soft error immunity. Compared with a previous cross-point Write 9T subthreshold SRAM cell reported in the literature, the proposed 9T SRAM cell offers comparable stability with improved Read performance and variation-tolerance. Monte Carlo simulations based on UMC 40nm Low-Power (40LP) technology indicate that the BL access time improves by 15.35% to 17.37%, and the variation (sigma of BL access time) improves by 5.12% to 9.22% for V-DD ranging from 0.3V to 0.6V. Based on a 72Kb SRAM macro design in UMC 40LP process, the proposed 9T cell achieves about 9% better chip access time (Ta) at SS corner for V-DD ranging from 0.3V to 0. 45V.
A Single-Ended Disturb-Free 9T Subthreshold SRAM With Cross-Point Data-Aware Write Word-Line Structure, Negative Bit-Line, and Adaptive Read Operation Timing Tracing
(2012-06-01)
Tu, Ming-Hsien
;
Lin, Jihi-Yu
;
Tsai, Ming-Chien
;
Lu, Chien-Yu
;
Lin, Yuh-Jiun
This paper presents a novel single-ended disturb-free 9T subthreshold SRAM cell with cross-point data-aware Write word-line structure. The disturb-free feature facilitates bit-inter-leaving architecture, which can reduce multiple-bit upsets in a single word and enhance soft error immunity by employing Error Checking and Correction (ECC) technique. The proposed 9T SRAM cell is demonstrated by a 72 Kb SRAM macro with a Negative Bit-Line (NBL) Write-assist and an adaptive Read operation timing tracing circuit implemented in 65 nm low-leakage CMOS technology. Measured full Read and Write functionality is error free with V-DD down to 0.35 V (similar to 0.15 V lower than the threshold voltage) with 229 KHz frequency and 4.05 mu W power. Data is held down to 0.275 V with 2.29 mu W Standby power. The minimum energy per operation is 4.5 pJ at 0.5 V. The 72 Kb SRAM macro has wide operation range from 1.2 V down to 0.35 V, with operating frequency of around 200 MHz for V-DD around/above 1.0 V.
Energy Efficient Bootstrapped CMOS Large RC-Load Driver Circuit for Ultra Low-Voltage VLSI
(2010)
Lu, Chien-Yu
;
Chuang, Ching-Te
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This paper presents an energy efficient bootstrapped CMOS driver to enhance switching speed for driving large RC load for ultra low-voltage CMOS VLSI. The proposed bootstrapped driver eliminates the leakage paths in the conventional bootstrapped driver to achieve more positive and negative boosted voltage levels and to allow the boosted nodes to maintain the boosted levels, thus improving boosting efficiency and enhancing the switching speed. Performance evaluation based on UMC 65nm low power technology (Vtn approximate to Vtp approximate to 0.5v) indicates that the proposed driver provides rising-delay improvement of 24%-56% and falling-delay improvement of 9%-30% at V-dd = 0.3 V for 1 to 10 segments of large distributed RC loading, as compared with the conventional bootstrapped driver consuming the same power. Although designed and optimized for ultra low-voltage operation, the proposed bootstrapped driver is shown to be advantageous at high supply voltage as well.