Browsing by Author "Lu, Chih-Yuan"

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A 2-bit/cell, maskless, self-aligned resistance memory with high thermal stability
(2007)
He, ChiaHua
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Lee, Ming-Daou
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Pan, Chen-Ling
;
Lai, Erb-Kun
;
Yao, Yeong-Der
We report the first demonstration of a multilevel cell (MLC) resistance device using a self-aligned WO, film prepared by plasma oxidation. The 2-bit/cell operation is achieved by applying a series of 1.5V programming pulses. The device shows high thermal stability and good data retention. The resistance change can be attributed to variable-range hopping and Ohmic transport mechanisms. This device has the potential for future low-voltage, 3-dimentioanl nonvolatile memory with multiple bits per layer. In addition, no additional mask is needed to form the self-aligned device.
A Comprehensive Study of 3-stage High Resistance State Retention Behavior for TMO ReRAMs from Single Cells to a Large Array
(2017-01-01)
Lin, Yu-Hsuan
;
Ho, Yung-Han
;
Lee, Ming-Hsiu
;
Wang, Chao-Hung
;
Lin, Yu-Yu
For the first time the retention of high resistance state (HRS) in resistive random access memory (ReRAM) is found to compose of three stages - extending tail-bits, distribution shift, and then distribution broadening. This work provides a comprehensive study on the HRS's retention behavior in WOx-based ReRAMs from single device characteristics to group distribution. Different from conventional activation energy (Ea) analysis, the mean and variance of the array distribution are presented to overcome the non-uniform Ea issue. Since the extracted Ea fits well with Vo(2+) (oxygen vacancy) migration characteristics, the three retention stages are suggested to be the competing results from the migration, recombination, and generation of the Vo(2+) and O2- in the gap region. A three-dimensional retention model with kinetic Monte Carlo simulator and trap-assisted tunneling conduction is proposed to discuss the dominating mechanism in different time and temperature scales. The mechanism for random telegraph noise is also included to illustrate the fluctuating nature of the HRS cells.
A Novel Hot-Electron Programming Method in a Buried Diffusion Bit-Line SONOS Memory by Utilizing Nonequilibrium Charge Transport
(2009-02-01)
Wang, Tahui
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Tang, Chun-Jung
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Li, C. -W.
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Lee, Chih Hsiung
;
Ou, T. -F
We propose a new hot-electron programming method with a low drain-to-source voltage in a buried-diffusion (BD) bit-line SONOS memory array. In this method, channel electrons are preaccelerated in a cell preceding a program cell. For a small bit-line width, some energetic electrons will traverse an n(+) BD region and enter a program cell with residual energy due to nonequilibrium transport. Our measurement result shows that this residual energy can significantly enhance hot-electron programming efficiency even at a V(ds) of 2.5 V. The concept of this method is verified by means of a Monte Carlo analysis. Our study shows that this method is more effective as a bit-line width reduces.
A Novel Random Telegraph Signal Method to Study Program/Erase Charge Lateral Spread and Retention Loss in a SONOS Flash Memory
(2011-03-01)
Ma, Huan-Chi
;
Chou, You-Liang
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Chiu, Jung-Piao
;
Chung, Yueh-Ting
;
Lin, Tung-Yang
A novel random telegraph signal (RTS) method is proposed to characterize the lateral distribution of injected charge in program and erase states in a NOR-type silicon-oxide-nitride-oxide-silicon Flash memory. The concept of this method is to use RTS to extract an oxide trap position in the channel and then to use the trap and RTS as internal probe to detect a local channel potential change resulting from injected charge during program/erase. By using this method, the lateral width of the injected charge-induced channel potential barrier is shown to be around 20 nm in channel hot electron (CHE) program. Our method also confirms that Channel Initiated Secondary ELectron (CHISEL) program has a broader injected charge distribution than CHE program. A mismatch of CHE program electrons and band-to-band tunneling erase holes is observed. Program-state V(t) retention loss models, charge vertical loss versus lateral migration, are reexamined by using this method. The polarity of a program-state charge distribution along the channel is explored within 10-20 program/erase cycles. Nitride charge vertical loss is verified by this method.
A Novel Varying-Bias Read Scheme for MLC and Wide Temperature Range TMO ReRAM
(2016-11)
Lin, Yu-Hsuan
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Lee, Ming-Hsiu
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Wu, Jau-Yi
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Lin, Yu-Yu
;
Lee, Feng-Ming
Resistance of transition metal oxide (TMO) resistive random access memory (ReRAM) depends sharply on temperature, resulting in drastic memory window loss at high temperature. Thus, it is difficult to design the ReRAM that can serve a wide range of operating conditions. It is especially challenging to achieve multi-level-cell (MLC) ReRAM because of the large temperature dependency. This letter investigates both the temperature and read bias dependencies of WOx ReRAM, and found both can be well understood by a modified space-charge limited conduction model. Using this model, we have designed a novel read scheme that varies the read bias according to the device temperature and compensates for the temperature effect on cell resistance. Since TMO ReRAM devices depend on defect states, cell-to-cell and cycle-to-cycle variations are naturally large. An algorithm is designed to address the variability. A 1-Mb WOx ReRAM array is fabricated to both characterize the bias and temperature dependencies and verify the new read scheme. A large and constant memory window is preserved for MLC across a wide temperature range (-40 degrees C-125 degrees C), suitable for high-reliability applications.
A Study of Blocking and Tunnel Oxide Engineering on Double-Trapping (DT) BE-SONOS Performance
(2015)
Lo, Roger
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Du, Pei-Ying
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Hsu, Tzu-Hsuan
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Wu, Chen-Jun
;
Guo, Jung-Yi
Double-trapping bandgap engineered SONOS (DT BE-SONOS) [1] was proposed to provide both fast erase speed and deep erase by means of a second nitride trapping layer and an additional blocking oxide on top of BE-SONOS. Although this provides excellent erase performance but the additional layers increase the EOT and subsequently the erase voltage, thus it is desirable to minimize their impact. This work investigates exhaustively the effect of thinning down the blocking layers. Since the ISPP and high temperature retention charge loss are mainly dominated by the ONO thickness of BE-SONOS below the blocking layers, reducing the blocking layer thickness has only minor impact on ISPP and retention. Moreover, erase saturation is determined by the dynamic balance of channel hole injection and gate electron injection. Experimental data show that reducing the thickness of the oxide between two trapping layers has little impact on erase saturation once the gate injected electrons are efficiently suppressed by the top most oxide. We have also investigated retention improvement by various oxides. By using HQ-SiO2 to replace the top tunnel ONO the trapped electron out-tunneling is reduced. Thus retention may be improved without increasing the effective oxide thickness.
A study of gate-sensing and channel-sensing (GSCS) transient analysis method - Part II: Study of the intra-nitride behaviors and reliability of SONOS-type devices
(2008-08-01)
Du, Pei-Ying
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Lue, Hang-Ting
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Wang, Szu-Yu
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Huang, Tiao-Yuan
;
Hsieh, Kuang-Yeu
For the first time, we can directly investigate the charge transport and intra-nitride behaviors of SONOS-type devices by exploiting the gate-sensing and channel-sensing (GSCS) method. Our results clearly indicate that for electron injection (+FN program), the electron centroid migrates from the bottom toward the nitride center, whereas for hole injection (-FN erase), holes first recombine with the bottom electrons and then gradually move upward. For the electron de-trapping processes under -V(G) stressing, the trapped electrons de-trap first from the bottom portion of nitride. We also develop a method to distinguish the electron de-trapping and hole injection erasing methods by comparing the erasing current density (J) versus the bottom oxide electric field (E). At short-term high-temperature baking, the electrons move from the top portion toward the bottom portion, and this intra-nitride transport becomes more significant for a thicker nitride. On the other hand, after long-term baking, the charge loss mainly comes from the bottom portion of nitride.
An oxide-buffered BE-MANOS charge-trapping device and the role of Al2O3
(2008)
Lai, Sheng-Chih
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Lue, Hang-Ting
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Liao, Chien-Wei
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Huang, Yu-Fong
;
Yang, Ming-Jui
The role of Al2O3 in MANOS device is critically examined, and we conclude that its primary function is to reduce gate injection during erase operation. By itself, Al2O3 cannot stop charge leakage from the charge-trapping nitride layer. Furthermore, Al2O3 provides no magic during the erase operation, and MANOS erases very slowly through charge de-trapping. BE-SONOS [1], with the band engineered ONO tunneling layers, provides efficient channel hole injection for erase. BE-MANOS [2] should be an ideal combination with fast erase and good reliability. However, it shows poor data retention. By inserting a SiO2 buffer layer between Al2O3 and the SiN storage layer, the oxide-buffered BE-MANOS shows good performance and good reliability. The EOT scalability is also investigated.
Analysis and Realization of TLC or even QLC Operation with a High Performance Multi-times Verify Scheme in 3D NAND Flash memory
(2018-01-01)
Lu, C. C.
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Cheng, C. C.
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Chiu, H. P.
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Lin, W. L.
;
Chen, T. W.
Feasibility of multi-times verify (MTV) scheme on triple-level cell (TLC) and quad-level cell (QLC) operations of charge-trap storage 3D NAND memories is investigated comprehensively. Results reveal that random telegraph noise (RTN) and program noise are the major factors affecting lower (LB) and upper boundaries (HB) of Vt distribution, respectively. Enlargement of operation window and reduction of ECC usage with MTV scheme to mitigate RTN-induced LB tail are demonstrated on TLC and QLC operations. In addition, the impact of program noise on HB Vt under various process conditions and ISPP steps is studied experimentally and also explained by our Monte Carlo simulator. Finally, program performance and reserved margin with and without MTV scheme applied on TLC and QLC operation are demonstrated.
<bold>Read Current Instability Arising from Random Telegraph Noise in Localized Storage, Multi-Level SONOS Flash Memory</bold>
(2006)
Gu, S. H.
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Li, C. W.
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Wang, Tahui
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Lu, W. P.
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Chen, K. C.
Program/erase cycling stress induced read current fluctuations arising from random telegraph noise (RTN) in a localized storage, multi-level nitride flash memory (SONOS) is explored. Our study shows that localized charge storage significantly enhances RTN. The amplitude of RTN varies in different program levels of a multi-level cell. The broadening of read current distribution due to RTN is characterized and modeled. Improvement of bottom oxide robustness can reduce the read current fluctuations.
Characterization and Monte Carlo analysis of secondary electrons induced program disturb in a buried diffusion bit-line SONOS flash memory
(2007)
Tang, Chun-Jung
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Li, C. W.
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Wang, Tahui
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Gu, S. H.
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Chen, P. C.
A new program disturb in a buried diffusion bit-line SONOS array is observed as a bit-line width is reduced. A multi-step Monte Carlo simulation is performed to explore the disturb mechanism. We find that the V, shift of a disturbed cell is attributed to impact ionization-generated secondary electrons in a neighboring cell when it is in programming. The effects of substrate bias, bit-line dimension and pocket implant on the program disturb are characterized and evaluated by a Monte Carlo simulation.
Characterization of nitride hole lateral transport in a charge trap flash memory by using a random telegraph signal method
(2017-07-17)
Liu, Yu-Heng
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Jiang, Cheng-Min
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Lin, Hsiao-Yi
;
Wang, Tahui
;
Tsai, Wen-Jer
We use a random telegraph signal method to investigate nitride trapped hole lateral transport in a charge trap flash memory. The concept of this method is to utilize an interface oxide trap and its associated random telegraph signal as an internal probe to detect a local channel potential change resulting from nitride charge lateral movement. We apply different voltages to the drain of a memory cell and vary a bake temperature in retention to study the electric field and temperature dependence of hole lateral movement in a nitride. Thermal energy absorption by trapped holes in lateral transport is characterized. Mechanisms of hole lateral transport in retention are investigated. From the measured and modeled results, we find that thermally assisted trap-to-band tunneling is a major trapped hole emission mechanism in nitride hole lateral transport. Published by AIP Publishing.
Chip-Level Characterization and RTN-Induced Error Mitigation beyond 20nm Floating Gate Flash Memory
(2018-01-01)
Lin, T. W.
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Ku, S. H.
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Cheng, C. H.
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Lee, C. W.
;
Ijen-Huang
Vt instability caused by random telegraph noise (RTN) in floating gate flash memories beyond 20nm is studied comprehensively. Experiments reveal that the RTN would cause Vt distribution with a kinked tail which re-distributes to a "Gaussian-like" shape rapidly and was measured by the self established Budget Product Tester (BPT). A Multi-Times Verify (MTV) algorithm to mitigate the statistical tail, thus enlarging operation window is also exhibited by BPT. In further, a probability model to portray the compact Vt distribution under MTV is proposed. Finally, the impact of MTV on lowering the requirement of Error-correcting code (ECC) bit is also demonstrated.
Cycling-Induced SET-Disturb Failure Time Degradation in a Resistive Switching Memory
(2015-02-01)
Chung, Yueh-Ting
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Su, Po-Cheng
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Cheng, Yu-Hsuan
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Wang, Tahui
;
Chen, Min-Cheng
A new degradation mode with respect to write-disturb failure time due to SET/RESET cycling in a tungsten oxide resistive random access memory is reported. In a crossbar array memory, we find that a write-disturb failure time in high resistance state reduces suddenly by several orders of magnitude after certain SET/RESET cycles. This abrupt degradation is believed due to the creation of a new soft breakdown path in a switching dielectric by cycling stress. Although a memory window still remains after the degradation, the occurrence probability of over-SET state increases significantly. This cycling-induced degradation mode imposes a serious constraint on the number of SET-disturb pulses and thus an endurance cycle number in a resistive switching memory.
Electric Field Induced Nitride Trapped Charge Lateral Migration in a SONOS Flash Memory
(2017-01)
Liu, Yu-Heng
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Jiang, Cheng-Min
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Chen, Wei-Chun
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Wang, Tahui
;
Tsai, Wen-Jer
We investigated electric field-induced trapped electron lateralmigration in a SONOS flash cell. The threshold voltage shift (Delta V-t) andgate-induceddrain leakage(GIDL) current were measured to monitor nitride electron movement in retention. We applied different voltages to the gate and the source/drain in retention to vary the vertical and lateral electric fields. Our study shows that: 1) GIDL current can be used tomonitor trapped charge lateralmigration and 2) nitride charge lateral migration exhibits strong dependence on the lateral electric field. Based on measured temperature and field dependence, a nitride trapped charge emission process via thermally assisted tunneling is proposed for electron lateral migration. The emission rates of thermally assisted tunneling, direct trap-to-band tunneling and Frenkel-Poole emission were compared.
Electric Field Induced Nitride Trapped Charge Lateral Migration in a SONOS Flash Memory
(2017-01)
Liu, Yu-Heng
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Jiang, Cheng-Min
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Chen, Wei-Chun
;
Wang, Tahui
;
Tsai, Wen-Jer
We investigated electric field-induced trapped electron lateralmigration in a SONOS flash cell. The threshold voltage shift (Delta V-t) andgate-induceddrain leakage(GIDL) current were measured to monitor nitride electron movement in retention. We applied different voltages to the gate and the source/drain in retention to vary the vertical and lateral electric fields. Our study shows that: 1) GIDL current can be used tomonitor trapped charge lateralmigration and 2) nitride charge lateral migration exhibits strong dependence on the lateral electric field. Based on measured temperature and field dependence, a nitride trapped charge emission process via thermally assisted tunneling is proposed for electron lateral migration. The emission rates of thermally assisted tunneling, direct trap-to-band tunneling and Frenkel-Poole emission were compared.
Error Characterization and ECC Usage Relaxation beyond 20nm Floating Gate NAND Flash Memory
(2018-01-01)
Ku, S. H.
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Lin, T. W.
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Cheng, C. H.
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Lee, C. W.
;
Chen, Ti-Wen
Endurance of floating gate flash memories at 19nm node and beyond is studied comprehensively. Experiments reveal that the random telegraph noise (RTN) would degrade the read margin with a tail, which quickly reshapes into a symmetric Gaussian form in a lightly-stressed state. After heavy stress, the lower part of tail would spread further while the upper part keeps roughly overlapped with that during fresh. This unique behavior, which was firstly measured by the self-established Budget Product Tester (BPT), can be explained by stress-induced hole trap creation. To investigate the impact of RTN on operation window, a novel algorithm of Multi-Times-Verify accompanied with the optimal Read-Retry (MTVR2) is proposed and validated by BPT. The advantage of MTVR2 to reduce the requirement of Error-Correcting Code (ECC) bit is demonstrated. Finally, the improvement of bit error rate (BER) in TLC operation with MTVR(2 )is also evaluated.
Excellent High Temperature Retention of TiOXNV ReRAM by Interfacial Layer Engineering
(2018-01-01)
Lin, Yu-Hsuan
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Lee, Dai-Ying
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Wang, Chao-Hung
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Lee, Ming-Hsiu
;
Ho, Yung-Han
Since the resistance switching of the transition metal oxide (TMO) resistive random access memory (ReRAM) is based on thc interaction between the oxygen ions and vacancies, the unintentional oxygen/vacancy reaction should be avoided during data retention. This work demonstrates significant improvements on the retention performance by inserting a Si layer in the TiO Ny ReRAM to block the diffusion of oxygen ions through the Ti/TiO,N interface. The mechanism and factors that influenced thc IIRS and LRS retention arc also studied. The retention performance of HRS is correlated with its RESET level while the LRS retention depends on the programming current. The proposed Ti/Si/TiO,N, ReRAMs can switch for more than 103 cycles from array testing results.
Excellent Resistance Variability Control of WOx ReRAM by a Smart Writing Algorithm
(2016)
Lin, Yu-Hsuan
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Wu, Jau-Yi
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Lee, Ming-Hsiu
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Wang, Tien-Yen
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Lin, Yu-Yu
TMO ReRAMs, being built on defect states, are intrinsically subject to variability. In this work, cell to cell variability is studied by applying write shots with different current and voltage for Forming, SET and RESET operation, respectively. We found the keys to eliminate tail bits consist of (1) longer write pulse, (2) higher write current and (3) higher write voltage. In order to optimize the performance of write speed, write power and device reliability, we developed a novel resistance control method using a smart writing algorithm. Compared to the conventional ISPP writing scheme, this smart writing algorithm covers much wider switching condition variability and cell-to-cell variation by controlling both current and voltage for ReRAM operation.
Extraction of nitride trap density from stress induced leakage current in silicon-oxide-nitride-oxide-silicon flash memory
(2006-10-16)
Gu, Shaw-Hung
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Wang, Tahui
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Lu, Wen-Pin
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Ku, Yen-Hui Joseph
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Lu, Chih-Yuan
The authors propose a technique to extract a silicon nitride trap density from stress induced leakage current in a polycrystalline silicon-oxide-nitride-oxide-silicon flash memory cell. An analytical model based on the Frenkel-Poole emission is developed to correlate a nitride trap density with stress induced leakage current. The extracted nitride trap density is 7.0x10(12) cm(-2) eV(-1). They find that nitride trapped charges have a rather uniform distribution in an energy range of measurement (similar to 0.2 eV). (c) 2006 American Institute of Physics.