Browsing by Author "Lu, Kuan-Cheng"

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Demonstration of 40-nm Channel Length Top-Gate p-MOSFET of WS2 Channel Directly Grown on SiOx/Si Substrates Using Area-Selective CVD Technology
(2019-12-01)
Chung, Yun-Yan
;
Lu, Kuan-Cheng
;
Cheng, Chao-Ching
;
Li, Ming-Yang
;
Lin, Chao-Ting
For high-volume manufacturing of 2-D transistors, area-selective chemical reaction deposition (CVD) growth is able to provide good-quality 2-D layers and may be more effective than exfoliation from bulk crystals or wet/dry transfer of large-area as-grown 2-D layers. We have successfully grown continuous and uniform WS2 film comprising around seven layers by area-selective CVD approach using patterned tungsten source/drain metals as the seeds. The growth mechanism is inferred and supported by the transmission electron microscope (TEM) images, as well. The first top-gate MOSFETs of CVD-WS2 channels on SiOx/Si substrates are demonstrated to have good short channel electrical characteristics: ON-/OFF-ratio of 10(6), a subthreshold swing of 97 mV/decade, and nearly zero drain-induced barrier lowering (DIBL).
Layer-Dependent and In-Plane Anisotropic Properties of Low-Temperature Synthesized Few-Layer PdSe2 Single Crystals
(2020-04-28)
Lu, Li-Syuan
;
Chen, Guan-Hao
;
Cheng, Hui-Yu
;
Chuu, Chih-Piao
;
Lu, Kuan-Cheng
Palladium diselenide (PdSe2), a peculiar noble metal dichalcogenide, has emerged as a new two-dimensional material with high predicted carrier mobility and a widely tunable band gap for device applications. The inherent in-plane anisotropy endowed by the pentagonal structure further renders PdSe2 promising for novel electronic, photonic, and thermoelectric applications. However, the direct synthesis of few-layer PdSe2 is still challenging and rarely reported. Here, we demonstrate that few-layer, single-crystal PdSe2 flakes can be synthesized at a relatively low growth temperature (300 degrees C) on sapphire substrates using low-pressure chemical vapor deposition (CVD). The well-defined rectangular domain shape and precisely determined layer number of the CVD-grown PdSe2 enable us to investigate their layer-dependent and in-plane anisotropic properties. The experimentally determined layer-dependent band gap shrinkage combined with first-principle calculations suggest that the interlayer interaction is weaker in few-layer PdSe2 in comparison with that in bulk crystals. Field-effect transistors based on the CVD-grown PdSe2 also show performances comparable to those based on exfoliated samples. The low-temperature synthesis method reported here provides a feasible approach to fabricate high-quality few-layer PdSe2 for device applications.