Browsing by Author "Lu, NP"

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3-disjoint gamma interconnection networks
(2003-05-15)
Chen, CW
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Lu, NP
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Chung, CP
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資訊工程學系
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Department of Computer Science
In this paper, we propose a new multistage interconnection network, called 3-disjoint gamma interconnection network (3DGIN). The 3DGIN is a modified gamma interconnection network that provides 3-disjoint paths to tolerate two switch or link faults between any source and destination pairs. The 3DGIN has lower hardware cost than GIN; furthermore, the routing and rerouting tags to generate 3-disjoint paths can be obtained in O(logN) time. To show the advantage features of 3DGIN, we also make a comparison between the gamma-related networks, the GIN, enhanced IADM, and 3DGIN. (C) 2002 Elsevier Science Inc. All rights reserved.
A fault-tolerant multistage combining network
(1996-04-10)
Lu, NP
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Chung, CP
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交大名義發表
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資訊科學與工程研究所
;
National Chiao Tung University
In this paper, we propose a solution to both fault tolerance and hot-spot contention problems in multiprocessor systems with multistage interconnection networks. Combining networks are known to be effective in handling hot-spot traffic. However, the fault tolerance capability of unique-path combining network is insufficient and must be enhanced. Thus, we use the chaining scheme, which provides alternate routing paths by connecting intrastage switching elements with a chain, to enhance the fault tolerance capability of combining network. As a result, we propose a chained combining network. Because of the bidirectionality of combining networks, we also develop routing procedures for the chained combining network. With slight modifications, these routing procedures can also be used in other multipath fault-tolerant combining networks. (C) 1996 Academic Press, Inc.
Applying stack simulation for branch target buffers
(2000-05-15)
Shiu, RM
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Lu, NP
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Chung, CP
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資訊科學與工程研究所
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Institute of Computer Science and Engineering
Branch target buffer (BTB) is widely used in modern microprocessor designs to reduce the penalties caused by branches. To evaluate the performance of a BTB, trace-driven simulation is often used. However, as the trace of a typical program is very large, the simulation time is often too long. To reduce the simulation time, we developed a stack simulation technique for BTB to evaluate many sets of design parameters in one simulation pass. Due to the fact that the prediction information in the BTB does not have the inclusion property - a property which makes the stack simulation work, we propose a state vector method to enumerate the prediction information for different sets of BTB design parameters to mimic the inclusion property. Simulation results show that the state vector method greatly reduces the simulation time. The speedup of the stack simulation for BTB proposed in this paper over the traditional BTB simulation is 4.68 in terms of simulation time when 13 sets of BTB design parameters are simulated in one simulation pass. (C) 2000 Elsevier Science Inc. All rights reserved.
Delayed precise invalidation - A software cache coherence scheme
(1996-09-01)
Hwang, TS
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Lu, NP
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Chung, CP
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交大名義發表
;
資訊工程學系
Software cache coherence schemes are very desirable in the design of scalable multiprocessors and massively parallel processors. The authors propose a software cache coherence scheme named 'delayed precise invalidation' (DPI). DPI is based on compiler-time markings of references and a hardware local invalidation of stale data in parallel and selectively. With a small amount of additional hardware and a small set of cache management instructions, this scheme provides more cacheability and allows invalidation of partial elements in an array, overcoming some inefficiencies and deficiencies of previous software cache coherence schemes.
Fault-tolerant gamma interconnection networks by chaining
(2000-03-01)
Chen, CW
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Lu, NP
;
Chen, TF
;
Chung, CP
;
資訊工程學系
The authors propose two single-fault-tolerant gamma interconnection networks. The first is a partially chained gamma interconnection network (PCGIN) with two disjoint paths between any source-destination pair. A PCGIN has the characteristics of one fault tolerance and destination tag routing, but backtracking may be necessary when a fault occurs. To eliminate the backtracking penalties of a PCGIN, a fully chained gamma interconnection network (FCGIN); that can at least tolerate one link or switch fault at each stage without backtracking, is also proposed FCGIN has the advantages of destination tag routing, lower hardware costs than a PCGIN, low fault penalty, and strong reroutability.
Memory system design in superscalar processing
(1995-09-01)
Lu, NP
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Chung, CP
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資訊科學與工程研究所
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Institute of Computer Science and Engineering
In this paper, we study the memory system design for superscalar processing. Benchmarking is used to examine the execution behavior of load/store instructions, such as load/store parallelism and memory load/store port utilization. It is found that the use of only a single load/store port forms a system bottleneck. A superscalar processor benefits from multiple load/store ports and system performance saturates with two load/store ports. The memory system must be carefully designed if multiple load/store ports are supported in a superscalar processor. Thus, we consider the design of the data cache subsystem. The data cache configurations we investigate include multiported cache, multibank cache, and duplicated cache. Through benchmarking, we find that the duplicated cache performs well in most benchmarks. Yet the cost of a duplicated cache is higher. In a superscalar multiprocessing environment, in order to properly maintain memory consistency, we must consider the load/store ordering of the processors. In superscalar processors, the load/store ordering may be in one of three forms: total ordering, load bypassing, and load forwarding. In this research, we conclude that to support the sequential consistency model, the load/store instructions must be totally ordered. Load bypassing and load forwarding are sufficient to support the processor consistency model.
Memory system design in superscalar processing
(1995-09-01)
Lu, NP
;
Chung, CP
;
交大名義發表
;
資訊科學與工程研究所
;
National Chiao Tung University
In this paper, we study the memory system design for superscalar processing. Benchmarking is used to examine the execution behavior of load/store instructions, such as load/store parallelism and memory load/store port utilization. It is found that the use of only a single load/store port forms a system bottleneck. A superscalar processor benefits from multiple load/store ports and system performance saturates with two load/store ports. The memory system must be carefully designed if multiple load/store ports are supported in a superscalar processor. Thus, we consider the design of the data cache subsystem. The data cache configurations we investigate include multiported cache, multibank cache, and duplicated cache. Through benchmarking, we find that the duplicated cache performs well in most benchmarks. Yet the cost of a duplicated cache is higher. In a superscalar multiprocessing environment, in order to properly maintain memory consistency, we must consider the load/store ordering of the processors. In superscalar processors, the load/store ordering may be in one of three forms: total ordering, load bypassing, and load forwarding. In this research, we conclude that to support the sequential consistency model, the load/store instructions must be totally ordered. Load bypassing and load forwarding are sufficient to support the processor consistency model.
Parallelism exploitation in superscalar multiprocessing
(1998-07-01)
Lu, NP
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Chung, CP
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資訊工程學系
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Department of Computer Science
To exploit more parallelism in programs, superscalar multiprocessor systems, which exploit both fine-grained and coarse-grained parallelism have been the trend in designing high-speed computing systems. Recently, the authors have developed a simulator for evaluating superscalar multiprocessor systems. This simulator models both a superscalar processor that can exploit instruction-level parallelism, and a shared-memory multiprocessor system that can exploit task-level parallelism. This simulator was used to run four applications chosen from the SPLASH-2 benchmark suite, and collected some performance data to investigate the parallelism exploitation capability of the superscalar multiprocessor systems in various configurations. It was observed that the instruction-level and task-level parallelism in programs can be exploited well by a moderate degree of superscalar processing and a high degree of multiprocessing. For example, the speedup of a 32-way multiprocessor with eight-issue processors can be over 200 relative to a single-issue uniprocessor.