Browsing by Author "Lu, Nan-Heng"

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Characteristics of Gate-All-Around Junctionless Poly-Si TFTs With an Ultrathin Channel
(2013-07-01)
Chen, Hung-Bin
;
Chang, Chun-Yen
;
Lu, Nan-Heng
;
Wu, Jia-Jiun
;
Han, Ming-Hung
This letter demonstrates for the first time junctionless (JL) gate-all-around (GAA) poly-Si thin-film transistors (TFTs) with ultrathin channels (2 nm). The subthreshold swing is 61 mV/decade and the ON/OFF current ratio is close to 10(8) because of the excellent gate controllability and ultrathin channel. The JL-GAA TFTs have a low drain-induced barrier lowering value of 6 mV/V, indicating greater suppression of the short-channel effect than in JL-planar TFTs. The cumulative distribution of electrical parameters in JL-GAA is small. Therefore, the proposed JL-GAA TFTs of excellent device characteristics along with simple fabrication are highly promising for future system-on-panel and system-on-chip applications.
High voltage characteristics of junctionless poly-silicon thin film transistors
(2013-09-16)
Cheng, Ya-Chi
;
Wu, Yung-Chun
;
Chen, Hung-Bin
;
Han, Ming-Hung
;
Lu, Nan-Heng
The breakdown voltage (V-BD) and breakdown mechanism of junctionless (JL) poly-Si thin film transistor (TFT) were compared to the conventional inversion-mode (IM) TFT using fabricated devices and 3D quantum-corrected hydrodynamic transport device simulation. The simulated results are correspondent with experimental ones. The analyses of electric field distributions in on-state show that the channel of JL devices can equally share the voltage like a resistor, because there are no junctions formed between channel and source/drain. The JL TFT shows excellent breakdown characteristics; the off-state V-BD of 53.4V is several times larger than V-BD of 9.5V in IM TFT with same device size. JL devices have large potential for high voltage power metal-oxide-semiconductor devices and circuit applications. (C) 2013 AIP Publishing LLC.
Temperature dependence of electronic behaviors in quantum dimension junctionless thin-film transistor
(2014-08-13)
Cheng, Ya-Chi
;
Chen, Hung-Bin
;
Han, Ming-Hung
;
Lu, Nan-Heng
;
Su, Jun-Ji
The high temperature dependence of junctionless (JL) gate-all-around (GAA) poly-Si thin-film transistors (TFTs) with 2-nm-thick nanosheet channel is compared with that of JL planar TFTs. The variation of SS with temperature for JL GAA TFTs is close to the theoretical value (0.2 mV/dec/K), owing to the oxidation process to form a 2-nm-thick channel. The bandgap of 1.35 eV in JL GAA TFTs by fitting experimental data exhibits the quantum confinement effect, indicating greater suppression of I-off than that in JL planar TFTs. The measured partial derivative V-th/partial derivative T of -1.34 mV/degrees C in JL GAA nanosheet TFTs has smaller temperature dependence than that of -5.01 mV/degrees C in JL planar TFTs.