Browsing by Author "Lu, P. Y."

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The Experimental Demonstration of the BTI-Induced Breakdown Path in 28nm High-k Metal Gate Technology CMOS Devices
(2014)
Hsieh, E. R.
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Lu, P. Y.
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Chung, Steve S.
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Chang, K. Y.
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Liu, C. H.
For the first time, the breakdown path induced by BTI stress can be traced from the RTN measurement. It was demonstrated on advanced high-k metal gate CMOS devices. RTN traps in the dielectric layers can be labeled as a pointer to trace the breakdown path. It was found that breakdown path tends to grow from the interface of HK/IL or IL/Si which is the most defective region. Two types of breakdown paths are revealed. The soft-breakdown path is in a shape like spindle, while the hard breakdown is like a snake-walking path. These two breakdown paths are reflected in a two slopes TDDB lifetime plot. These new findings on the breakdown-path formation will be helpful to the understanding of the reliability in HK CMOS devices.
The Observation of BTI-induced RTN Traps in Inversion and Accumulation Modes on HfO2 High-k Metal Gate 28nm CMOS Devices
(2014-01-01)
Wu, P. C.
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Hsieh, E. R.
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Lu, P. Y.
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Chung, Steve S.
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Chang, K. Y.
A comprehensive analysis on the BTI induced RTN traps in high-k(HK) CMOS devices have been investigated in inversion (inv.) and accumulation (acc.) modes. The combination of two modes for RTN measurement provides a wide range of energy window in high-k gate dielectric, in which a simple extraction method of RTN analysis has been adopted to analyze the gate dielectric dual-layer of advanced HK devices. The results show that inversion mode measurement can only identify the RTN traps in the channel region, which is related to the V-th degradation. While, accumulation mode may detect the traps inside the gate-drain overlap region which provides better understanding of GIDL current. This basic understanding is of critical important to the quality development of HK gate dielectrics in advanced CMOS technologies.
The RTN Measurement Technique on Leakage Path Finding in Advanced High-k Metal Gate CMOS Devices
(2015)
Hsieh, E. R.
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Lu, P. Y.
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Chung, Steve S.
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Ke, J. C.
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Yang, C. W.
In this paper, the evolution of BTI induced leakage paths has been evaluated by I-g-RTN technique and demonstrated on HK/MG CMOS devices. First, RTN measurement has been elaborated to identify the location of traps and their correlation to the leakage current. Then, the measured gate current transient can he used to analyze the formation of breakdown path. The results show that the evolution of leakage paths can be divided into three stages, i.e., (I) the early stage- only gate leakage and discrete RTN traps are observed, (2) the middle stage- the traps interacting with the percolation paths and exhibits a multi-level current variation, and (3) the last stage- the formation of breakdown path. These findings provide useful information on the understanding of gate dielectric breakdown in high-k CMOS devices.