Browsing by Author "Lu, TY"

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A 5-GHz direct-conversion receiver with I/Q phase and gain error calibration
(2005)
Chen, WZ
;
Lee, TL
;
Lu, TY
;
電機學院
;
College of Electrical and Computer Engineering
This paper describes the design of a 5GHz direct conversion receiver with phase and gain errors calibration for WLAN application. Integrated both LNA and mixer in a single chip, the conversion gain of the RF receiver is switch-able to compromise between linearity and noise performance. In addition, calibration schemes are proposed to compensate gain and phase errors in the I/Q signal paths. By means of this technique, the measured phase error is reduced to be less than 0.6 degrees and gain error less than 0.2 dB. The receiver provides a conversion gain of 28.2 dB in the high gain mode and 11.6 dB in the low gain mode within the signal bandwidth. The overall noise figure is 6.4dB in the high gain mode, and the third-order input intercept point (IIP3) is about -6.8dBm in the low gain mode. Implemented in a 0.18-mu m CMOS technology, it consumes 37.4 mW from a 1.8 V supply. Chip area is 1.64 mm(2).
Mobility enhancement in local strain channel nMOSFETs by stacked a-Si/poly-Si gate and capping nitride
(2005-04-01)
Lu, TY
;
Chao, TS
;
交大名義發表
;
National Chiao Tung University
A local strained channel nMOSFET has been fabricated by a stress control technique utilizing a stacked a-Si/poly-Si gate and a SiN capping layer. It is found that the transconductance (G(M)) of nMOSFETs increases as the thickness of a-Si is increased. We also found that the G(M) of devices with the SiN capping layer exhibits a 17% increase compared to that of its counterparts. The stacked gate a-Si/poly-Si with the capping layer can improve the G(M) further to 29% more than the single-poly-Si gate structure without SiN capping layer.
Mobility enhancement in local strain channel nMOSFETs by stacked a-Si/poly-Si gate and capping nitride
(2005-04-01)
Lu, TY
;
Chao, TS
;
電子物理學系
;
Department of Electrophysics
A local strained channel nMOSFET has been fabricated by a stress control technique utilizing a stacked a-Si/poly-Si gate and a SiN capping layer. It is found that the transconductance (G(M)) of nMOSFETs increases as the thickness of a-Si is increased. We also found that the G(M) of devices with the SiN capping layer exhibits a 17% increase compared to that of its counterparts. The stacked gate a-Si/poly-Si with the capping layer can improve the G(M) further to 29% more than the single-poly-Si gate structure without SiN capping layer.