Browsing by Author "Lu, Tai-You"

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A 160-GHz Frequency-Translation Phase-Locked Loop With RSSI Assisted Frequency Acquisition
(2014-06-01)
Chen, Wei-Zen
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Lu, Tai-You
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Wang, Yan-Ting
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Jian, Jhong-Ting
;
Yang, Yi-Hung
A 160-GHz frequency-translation PLL with tuning range from 156.4 GHz to 159.2 GHz is presented. Sub-THz 1/9 prescaler is replaced by a 3rd harmonic mixer incorporating a frequency tripler for frequency down conversion. A transformer-based VCO is utilized to alleviate capacitive and resistive load associated with varactor and succeeding buffer stages. Frequency acquisition is assisted by received signal strength indicator (RSSI) for automatic frequency sweeping and fast locking. Fabricated in 65 nm CMOS technology, the chip size is 0.92 mm(2). The PLL locking time is less than 3 mu s. This chip drains 24 mW from a 1.2 V power supply.
A 2.4 GHz Reference-Less Receiver for 1 Mbps QPSK Demodulation
(2012-03-01)
Chen, Wei-Zen
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Lu, Tai-You
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Ou, Wei-Wen
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Chou, Shun-Tien
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Yang, Song-Yu
A 2.4 GHz reference-less single chip wireless receiver for 1 Mbps QPSK demodulation is presented. The receiver accomplishes LO carrier recovery and data demodulation directly from the RF received signal without resort to resonator based reference, such as crystal oscillator. Integrating LNA, mixer, LO carrier recovery loop, postamplifier, and digital demodulator on a single chip, the total power consumption is 20.4 mW. The measured phase noise from a recovered carrier at 2.432 GHz is about -111 dBc/Hz at 1 MHz offset. The chip size is 1.75 x 1.55 mm(2).
A 2.4 GHz Reference-less Wireless Receiver for 1Mbps QPSK Demodulation
(2010)
Chen, Wei-Zen
;
Ou, Wei-Wen
;
Lu, Tai-You
;
Chou, Shun-Tien
;
Yang, Song-Yu
A 2.4 GHz reference-less single chip wireless receiver for 1Mbps QPSK demodulation is presented. The receiver accomplishes LO carrier recovery and data demodulation directly from the received RF signal without resort to resonator based reference, such as crystal oscillator. Integrating LNA, mixer, LO carrier recovery loop, post amplifier, and digital demodulator on a single chip, the total power consumption is 20.4mW. The measured phase noise from a recovered carrier at 2.432 GHz is about -112 dBc/Hz at 1 MHz offset. The chip size is 1.75 x 1.55 mm(2).
A 38/114 GHz Switched-Mode and Synchronous Lock Standing Wave Oscillator
(2011-01-01)
Lu, Tai-You
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Chen, Wei-Zen
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
This letter presents a 38/114 GHz switched-mode standing wave oscillator (SWO) capable of synchronous locking. Triple output frequency can be excited by digital control of different mode operations. The experimental prototype was fabricated using a low leakage 65 nm 1P9M triple-well CMOS technology. Incorporating a synchronous lock scheme, the measured phase noise from a 38 GHz carrier before and after the phase locked at 1 MHz offset are -102 dBc/Hz and -120 dBc/Hz, respectively. For the mode 1 operation at 38 GHz and mode 3 operation at 114 GHz, the experimental prototype consumes 4 and 20 mA, respectively, under a 1.2 V biasing voltage and with a chip size of 720 x 880 mu m(2).
A 60-GHz, 14% Tuning Range, Multi-Band VCO with a Single Variable Inductor
(2008)
Yu, Chi-Yao
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Chen, Wei-Zen
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Wu, Chung-Yu
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Lu, Tai-You
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電子工程學系及電子研究所
This paper presents the design of a 60-GHz, 14% tuning range VCO with a single variable inductor (VID). By employing the proposed frequency tuning scheme, wide-tuning range as well as multi-band operations are achieved without sacrificing its operating frequency. Fabricated in a 90-nm CMOS process, the VCO is capable of covering frequency range from 53.1 to 61.3 GHz. The measured phase noise from a 61.3 GHz carrier is about -118.75 dBc/Hz at 10-MHz offset, and the output power is -6.6 dBm. The VCO core dissipates 8.7 mW from a 0.7-V supply. Chip size is 0.28 x 0.36 mm(2).
A 7.1 mW, 10 GHz All Digital Frequency Synthesizer With Dynamically Reconfigured Digital Loop Filter in 90 nm CMOS Technology
(2010-03-01)
Yang, Song-Yu
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Chen, Wei-Zen
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Lu, Tai-You
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A 10 GHz all digital frequency synthesizer (ADPLL) with dynamic digital loop filter is presented. Governed by a proposed locking process monitor (LPM), the digital loop filter is automatically reconfigured during the frequency acquisition and phase tracking process. The loop bandwidth is also self-adjusted during the locking process so as to achieve fast lock and low noise simultaneously. A skew-compensated phase accumulator is proposed for high speed operation, which preserves the advantages of low power dissipation while eliminating the accumulated timing skew issue. With less than 7 mu s locking time, the measured rms jitter from a 9.92 GHz carrier is about 0.9 ps. The ADPLL core consumes 7.1 mW from a 1 V supply, and the digital I/O cells drains 2.7 mW from a 3.3 V supply for chip measurement. Implemented in a 90 nm CMOS technology, the core area is only 0.352 mm(2).
Wide Tunning Range 60 GHz VCO and 40 GHz DCO Using Single Variable Inductor
(2013-02-01)
Lu, Tai-You
;
Yu, Chi-Yao
;
Chen, Wei-Zen
;
Wu, Chung-Yu
;
電子工程學系及電子研究所
This paper presents a 60 GHz, 16% tuning range VCO, and a 40 GHz, 18 bits, 14% tuning range DCO incorporating variable inductor (VID) techniques. The variable inductor, consisting of a transformer and a variable resistor, is tunable by adjusting its resistor. By employing the proposed frequency tuning scheme, wide-tuning range as well as multi-band operation are achieved without sacrificing their operating frequencies. To verify the operation principles, the VCO and DCO are both fabricated in 90 nm CMOS technology. The tuning range of VCO is from 52.2 GHz to 61.3 GHz. The measured phase noise from a 61.3-GHz carrier is about -118.75 dBc/Hz at 10-MHz offset, and the output power is -6.6 dBm. It dissipates 8.7 mW from a 0.7-V supply, and the chip size is 0.28 x 0.36 mm(2). On the other hand, the DCO is capable of covering frequency range from 37.6 GHz to 43.4 GHz. The measured phase noise from a 43 GHz carrier is about -109 dBc/Hz at 10-MHz offset, and the output power is -11 dBm. The DCO core dissipates 19 mW from a 1.2-V supply. Chip size is 0.5 x 0.15 mm(2).