Browsing by Author "Lu, Tien-Lin"

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Anisotropic Grain Growth in (111) Nanotwinned Cu Films by DC Electrodeposition
(2020-01-01)
Lu, Tien-Lin
;
Shen, Yu-An
;
Wu, John A.
;
Chen, Chih
;
材料科學與工程學系
We have reported a method of fabricating (111)-orientated nanotwinned copper (nt-Cu) by direct current electroplating. X-ray analysis was performed for the samples annealed at 200 to 350 degrees C for an hour. X-ray diffraction indicates that the (200) signal intensity increases while (111) decreases. Abnormal grain growth normally results from transformation of surface energy or strain energy density. The average grain size increased from 3.8 mu m for the as-deposited Cu films to 65-70 mu m after the annealing at 250 degrees C for 1 h. For comparison, no significant grain growth behavior was observed by random Cu film after annealing for an hour. This research shows the potential for its broad electric application in interconnects and three-dimensional integrated circuit (3D IC) packaging.
Extremely anisotropic single-crystal growth in nanotwinned copper
(2014-10-01)
Lu, Chia-Ling
;
Lin, Han-Wen
;
Liu, Chien-Min
;
Huang, Yi-Sa
;
Lu, Tien-Lin
By electroplating of nearly unidirectionally < 111 >-oriented nanotwinned and fine-grained Cu on a Si wafer surface followed by annealing at 400-500 degrees C for up to 1 h, we grew many extremely large < 100 >-oriented single crystals of Cu with sizes ranging from 200 to 400 mu m. By patterning and annealing the nanotwinned Cu films, we grew an array of < 100 >-oriented single crystals of Cu with sizes ranging from 25 to 100 mu m on Si. In comparison, single-crystal nano-wire growth is a one-dimensional anisotropic growth process, in which the growth along the axial direction is much faster than in the radial direction. We report here a bulk-type two-dimensional crystal growth of an array of numerous < 100 >-oriented single crystals of Cu on Si. This growth process has the potential for microbump applications in three-dimensional integrated circuit-packaging technology for hand-held consumer electronic products.
Fabrication and Characterization of < 100 >-Oriented Quasi-single Crystalline Cu Lines
(2020-03-01)
Lu, Tien-Lin
;
Wu, John A.
;
Chen, Chih
;
材料科學與工程學系
;
Department of Materials Science and Engineering
Nanotwinned copper (nt-Cu) films with < 111 > crystal orientation were electroplated on Si wafers by pulse plating, with original grain size of similar to 1.4 mu m. By patterning and annealing the nt-Cu film at 450-500 degrees C for 1 h, we can grow a large number of < 100 >-oriented quasi-single crystal Cu lines that are 200 and 500 pm in length and 60 pm in width. We perform anisotropic grain growth on a Si substrate to fabricate quasi-single crystal Cu lines array of < 100 > crystal orientation. These large < 100 > Cu single crystals may have potential applications as interconnects in three-dimensional integrated circuit technology.
Fabrication of (111) nanotwinned Cu and its applications in interconnects of microelectronic devices
(2016)
Chen, Chih
;
Liu, Chien-Min
;
Lu, Tien-Lin
;
Lin, Han-wen
;
Chu, Yi-Cheng
Fabrication of arrays of (100) Cu under-bump-metallization for 3D IC packaging
(2015)
Chiu, Wei-Lan
;
Lu, Chia-Ling
;
Lin, Han-Wen
;
Liu, Chien-Min
;
Huang, Yi-Sa
Due to the thousands of microbumps on a chip for 3D ICs, the precise control of the microstructure of all the material is required. The nearly < 111 >-oriented nanotwinned and fine-grained Cu was electroplated on a Si wafer surface and annealed at 400-500 C for 1 h, many extremely large < 100 > oriented Cu crystals with grain sizes ranging from 200 to 400 um were obtained. The < 111 >-oriented Cu grains were transformed into super-large < 100 >-oriented grains after the annealing. In addition, we patterned the < 111 >-oriented Cu films into pad arrays of 25 to 100 um in diameter and annealed the nanotwinned Cu pads with same conditions. An array of < 100 >-oriented single crystals Cu pads can be obtained. Otherwise, single-crystal nano wire growth displays a process by one-dimensional anisotropic growth, in which the growth along the axial direction is much faster than in the radial direction. This study reported here a bulk-type two-dimensional crystal growth of an array of numerous < 100 >-oriented single crystals of Cu on Si. The growth process in 3D IC has the potential for microbump applications packaging technology.
Iridium Nanocrystal Thin-Film Transistor Nonvolatile Memory with Si(3)N(4)/SiO(2) Stack of Asymmetric Tunnel Barrier
(2011-05-01)
Wang, Terry Tai-Jui
;
Lu, Tien-Lin
;
Wu, Chien-Hung
;
Liu, Yu-Cheng
;
Hung, Shih-Wei
Iridium nanocrystals (Ir-NCs) lying on the Si(3)N(4)/SiO(2) tunneling layer have been demonstrated and Ir-NC-assisted thin-film transistor nonvolatile memory devices were successfully developed. Results show that Ir-NCs with a number density of similar to 6 x 10(11) cm(-2) and a particle diameter of 4 to 12 nm can successfully be fabricated as charge trapping centers. Owing to the asymmetric SiO(2)/Si(3)N(4) tunneling layer that increases programming/erasing efficiency, a significant memory window of 5.5 V has potential to be applied to multibit memory devices. Furthermore, after 10(4) s, the memory window is still about 4.0 V in logic states. (C) 2011 The Japan Society of Applied Physics
Iridium Nanocrystal Thin-Film Transistor Nonvolatile Memory with Si3N4/SiO2 Stack of Asymmetric Tunnel Barrier
(2011-05-01)
Wang, Terry Tai-Jui
;
Lu, Tien-Lin
;
Wu, Chien-Hung
;
Liu, Yu-Cheng
;
Hung, Shih-Wei
Iridium nanocrystals (Ir-NCs) lying on the Si3N4/SiO2 tunneling layer have been demonstrated and Ir-NC-assisted thin-film transistor nonvolatile memory devices were successfully developed. Results show that Ir-NCs with a number density of similar to 6 x 10(11) cm(-2) and a particle diameter of 4 to 12 nm can successfully be fabricated as charge trapping centers. Owing to the asymmetric SiO2/Si3N4 tunneling layer that increases programming/erasing efficiency, a significant memory window of 5.5 V has potential to be applied to multibit memory devices. Furthermore, after 10(4) s, the memory window is still about 4.0 V in logic states. (C) 2011 The Japan Society of Applied Physics
Nickel Nanocrystals Embedded in Metal-Alumina-Nitride-Oxide-Silicon Type Low-Temperature Polycrystalline-Silicon Thin-Film Transistor for Low-Voltage Nonvolatile Memory Application
(2011-06-01)
Wang, Terry Tai-Jui
;
Liu, Yu-Cheng
;
Wu, Chien-Hung
;
Lu, Tien-Lin
;
Hsieh, Ing-Jar
In this work, a nickel nanocrystal (Ni-NC) assisted metal-alumina-nitride-oxide-silicon (MANOS) thin-film transistor (TFT) nonvolatile memory (NVM) was fabricated by a standard low temperature polycrystalline silicon (LTPS) TFT process. The size range and density of Ni-NCs were approximately 5-13 nm and 5 x 10(11) cm(-2), respectively. The programming/erasing (P/E) voltages are decreased down to -10 and +8 V, respectively, by the Fowler-Nordheim tunneling mechanism from gate injection. In this P/E voltage condition, a large memory window (similar to 4.2 V) was observed by current-voltage measurement. Then, the speed and voltages of P/E were measured and discussed completely. The data retention of the Ni-NC assisted MANOS-LTPS-TFT-NVM is extracted to be 1.62 V of memory window after 10(4) s. (C) 2011 The Japan Society of Applied Physics