Browsing by Author "Lu, Tsung Yi"

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Enhancement of Stress-Memorization Technique on nMOSFETs by Multiple Strain-Gate Engineering
(2009)
Lu, Tsung Yi
;
Wang, Chin Meng
;
Chao, Tien-Sheng
;
電子物理學系
;
Department of Electrophysics
An enhanced stress memorization-technique that utilizes a strain proximity free technique (SPFT) and a stacked-gate structure has been demonstrated by multiple strain-gate engineering. The electron mobility of n-channel metal-oxide semiconductor field effect transistors (nMOSFETs) with SPFT exhibit a 16% increase compared to that of counterpart techniques. SPFT avoids the limitation of stressor volume for performance improvement in high-density complementary metal oxide semiconductor circuits. We also found that optimization of stacked, random poly-Si-grain gate structure in combination with SPFT can improve mobility further to 22% more than a single poly-Si gate structure without SPFT.
Impacts of Multiple Strain-Gate Engineering on a Zero-Temperature-Coefficient Point
(2013-04-01)
Chang, Tien-Shun
;
Lu, Tsung Yi
;
Chao, Tien-Sheng
;
交大名義發表
;
National Chiao Tung University
The impacts of zero-temperature-coefficient (ZTC) points of various strained devices is presented in this letter. The current and mobility are reduced at high temperature by phonon scattering. The degree of mobility reduction becomes severe on devices with multiple strain-gate engineering. The reduction of mobility becomes severe as a result of impurity scattering, which results from gate implantation impurities. The ZTC point is decreased by multiple strain-gate engineering due to the decreased Vth.
Temperature Dependence of Electron Mobility on Strained nMOSFETs Fabricated by Strain-Gate Engineering
(2012-07-01)
Chang, Tien-Shun
;
Lu, Tsung Yi
;
Chao, Tien-Sheng
;
電子物理學系
;
Department of Electrophysics
An effective electron mobility improvement that uses strain-proximity-free technique (SPFT) has been demonstrated using strain-gate engineering. The electron mobility of nMOSFETs with SPFT exhibits a 15% increase over that of counterpart techniques. The preamorphous layer (PAL) gate structure on the SPFT showed a further performance boost. The electron mobility exhibits a 52% improvement in nMOSFET using a combination of SPFT and PAL gate structure. Furthermore, the gain in electron mobility in the SPFT in combination with PAL gate structure decreases at high temperatures. Gate dielectric interface states and ionized gate impurities inducing carrier scattering will play important roles when operating devices under high-temperature conditions.