Browsing by Author "Lu, Tsung-Che"

Now showing 1 - 7 of 7

A 0.5V 1KS/s 2.5nW 8.52-ENOB 6.8fJ/Conversion-Step SAR ADC for Biomedical Applications
(2011)
Lu, Tsung-Che
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Van, Lan-Da
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Lin, Chi-Sheng
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Huang, Chun-Ming
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資訊工程學系
A low-FOM SAR ADC using the leakage reduction bootstrapped switch (LRBS) to achieve a satisfactory ENOB and using a low-power approach with a low voltage, low sampling rate, and low-DAC-capacitance structure is presented for biomedical applications. LRBS is proposed to alleviate the leakage caused by the low-power approach to increase SNDR and ENOB. From the measurement results, the 0.18 mu m CMOS prototype chip with the total DAC capacitance of 2.765pF consumes 2.5nW and achieves a SNDR of 53.05dB under a 0.5V supply voltage at 1KS/s with a Nyquist input. The resulting FOM is 6.8fJ/conversion-step.
Cost-Effective and Variable-Channel FastICA Hardware Architecture and Implementation for EEG Signal Processing
(2016-01-01)
Van, Lan-Da
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Huang, Po-Yen
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Lu, Tsung-Che
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資訊工程學系
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Department of Computer Science
This paper proposes a cost-effective and variable-channel floating-point fast independent component analysis (FastICA) hardware architecture and implementation for EEG signal processing. The Gram-Schmidt orthonormalization based whitening process is utilized to eliminate the use of the dedicated hardware for eigenvalue decomposition (EVD) in the FastICA algorithm. The proposed two processing units, PU1 and PU2, in the presented FastICA hardware architecture can be reused for the centering operation of preprocessing and the updating step of the fixed-point algorithm of the FastICA algorithm, and PU1 is reused for Gram-Schmidt orthonormalization operation of preprocessing and fixed-point algorithm to reduce the hardware cost and support 2-to-16 channel FastICA. Apart from the FastICA processing, the proposed hardware architecture supports re-reference, synchronized average, and moving average functions. The cost-effective and variable-channel FastICA hardware architecture is implemented in 90 nm 1P9M complementary metal-oxide-semiconductor (CMOS) process. As a result, the FastICA hardware implementation consumes 19.4 mW at 100 MHz with a 1.0 V supply voltage. The core size of the chip is 1.43 mm(2). From the experimental results, the presented work achieves satisfactory performance for each function.
FPGA-Oriented Real-Time EMD-Based Breath Signal Processing System on ARM11 MPCore Platform
(2018-01-01)
Lu, Tsung-Che
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Lin, Chien-Liang
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Chen, Pei-Yu
;
Lan-Da Van
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資訊工程學系
In this paper, a complete FPGA-oriented real-time empirical mode decomposition (EMD)-based breath signal processing system on ARM11 MPCore platform is developed. The system consists of three subsystems including biomedical signal acquisition, FPGA-oriented EMD accelerator and EMD processing result display. In this work, the previous published multiple stopping criteria and high IMFs Application Specific Integrated Circuit (ASIC)-oriented EMD accelerator is deployed to FPGA of ARM 11 MPCore platform such that the computation time of the overall system can he reduced. An external SRAM architecture in ARM 11 MPCore platform is adopted to process a large amount of data. The three subsystems are connected by a high speed internet such that real time data transportation is achieved. From the evaluation results, for 10K data size, the FPGA-oriented EMD accelerator can speed up by 29.21 times, 20.20 times, and 15.47 times compared with ARM11 processor running single core, dual cores, and four cores, respectively.
HARDWARE-ORIENTED MEMORY-LIMITED ONLINE FASTICA ALGORITHM AND HARDWARE ARCHITECTURE FOR SIGNAL SEPARATION
(2019-01-01)
Van, Lan-Da
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Lu, Tsung-Che
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Jung, Tzyy-Ping
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Wang, Jo-Fu
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資訊工程學系
This paper presents a hardware-oriented memory-limited online FastICA algorithm and its hardware architecture and implementation for eight-channel electroencephalogram ( EEG) signal separation. The online algorithm integrates the data overlapping, garbage detection, channel permutation, and momentum-controlled weight update schemes to stabilize the order of the decomposed source signals across time. This study also realizes the algorithm into a hardware architecture and implementation with a core area of 1.469x1.469 mm(2) in a TSMC 90 nm process. The resulting power dissipation for eight-channel EEG signal separation is 65 mW@100 MHz at 1V.
Implementation of a Human-Centric GUI for Next-Generation Intensive Care Unit
(2014-01-01)
Lu, Tsung-Che
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Hsu, Shang-Hwa
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Tzeng, Sing-Jia
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Chang, Che-Ming
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Van, Lan-Da
In the intensive care unit (ICU), the situations of the critical patients vary rapidly. To give the patient the necessary medical treatment, the medical staffs need to response in no time. However, making the diagnosis is not easy since there is tremendous information to be processed in ICU. In this paper, a prototype human-centric graphical user interface (GUI) based on ecological interface design (EID) is implemented by C# that is compatible with Microsoft Windows system. The human-centric GUI integrates the necessary information and will help the medical staffs to interpret them efficiently. The waveforms of artificial vital signs are displayed to show the variations of those signs instantly. Besides, the GUI can display the heart/lung/kidney indicators in radar charts to assist medical staffs aware of abnormal indicators in a visual way.
Multiple Stopping Criteria and High-Precision EMD Architecture Implementation for Hilbert-Huang Transform
(2014-01-01)
Lu, Tsung-Che
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Chen, Pei-Yu
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Yeh, Shih-Wei
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Van, Lan-Da
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資訊工程學系
In this work, a multiple stopping criteria and high-recision empirical mode decomposition (EMD) hardware architecture implementation is proposed for Hilbert-Huang transform (HHT) in biomedical signal processing. The proposed architecture can support multiple stopping criteria including the constant criteria, the SD criteria and the ratio criteria. The 38-bit floating point precision is adopted in this work to support 10 IMF components with enough accuracy. The off-chip memory architecture is adopted to increase the processing capacity. By the pipelined cubic spline coefficient unit (PCSCU), the computation time can be reduced. The proposed EMD hardware architecture is implemented in TSMC 90 nm CMOS process with the core area of 4.47 mm(2) at the operating frequency of 40 MHz. The post-layout simulation result shows that our work with the constant criterion can speed up the performance 50.4 times compared to the software computation on a single core of ARM11 for 2K data size breathing signals.
Type-4 2-D Diagonal and Four-Fold Rotational Symmetry Digital Filter Architectures
(2018-01-01)
Van, Lan-Da
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Lu, Tsung-Che
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Chen, Pei-Yu
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Reddy, Hari C.
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資訊工程學系
In this paper, Type-4 two-dimensional (2-D) separable denominator IIR filter architecture is studied. This structure has a critical path of one multiplication and three additions. Using this Type-4 2-D separable denominator IIR filter architecture, three new 2-D IIR filter structures with diagonal and four-fold rotational symmetries are given. These structures have a critical path of one multiplication and four additions. Further, using a different coefficient constraint, a new Type-3 2-D diagonal symmetry IIR filter architecture with a critical path of one multiplication and two additions is obtained. In all, four different 2-D IIR filter architectures with diagonal and four-fold rotational symmetries are presented.