Browsing by Author "Lu, W. P."

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<bold>Read Current Instability Arising from Random Telegraph Noise in Localized Storage, Multi-Level SONOS Flash Memory</bold>
(2006)
Gu, S. H.
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Li, C. W.
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Wang, Tahui
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Lu, W. P.
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Chen, K. C.
Program/erase cycling stress induced read current fluctuations arising from random telegraph noise (RTN) in a localized storage, multi-level nitride flash memory (SONOS) is explored. Our study shows that localized charge storage significantly enhances RTN. The amplitude of RTN varies in different program levels of a multi-level cell. The broadening of read current distribution due to RTN is characterized and modeled. Improvement of bottom oxide robustness can reduce the read current fluctuations.
Cell Endurance Prediction from a Large-area SONOS Capacitor
(2009)
Lee, C. H.
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Tu, W. H.
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Gu, S. H.
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Wu, C. W.
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Lin, S. W.
Endurance considerations induced by the degadation of top and bottom oxides are proposed for a SONOS memory. First, a correlation is found between the widespread C-V curves induced by interface generation and cycling numbers (cyc. #). Unlike V-FB (accumulation region), V-T (inversion region) shows a much severe shift. Inter-face state (N-it) is identified as a key factor even when a 2nm bottom oxide is used. Moreover, charge to breakdown (Q(BD)) for an ONO capacitor under positive and negative constant current stress (CCS) is investigated. Our study reveals that QBD of such stacks strongly depends on the top oxide thickness. A field enhancement induced by charges in a trapping nitride layer is the root cause. Based on Weibull statistics, the risk of dielectric breakdown for both blocking layers is then evaluated.
Characterization and Monte Carlo analysis of secondary electrons induced program disturb in a buried diffusion bit-line SONOS flash memory
(2007)
Tang, Chun-Jung
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Li, C. W.
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Wang, Tahui
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Gu, S. H.
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Chen, P. C.
A new program disturb in a buried diffusion bit-line SONOS array is observed as a bit-line width is reduced. A multi-step Monte Carlo simulation is performed to explore the disturb mechanism. We find that the V, shift of a disturbed cell is attributed to impact ionization-generated secondary electrons in a neighboring cell when it is in programming. The effects of substrate bias, bit-line dimension and pocket implant on the program disturb are characterized and evaluated by a Monte Carlo simulation.
Chip-Level Characterization and RTN-Induced Error Mitigation beyond 20nm Floating Gate Flash Memory
(2018-01-01)
Lin, T. W.
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Ku, S. H.
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Cheng, C. H.
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Lee, C. W.
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Ijen-Huang
Vt instability caused by random telegraph noise (RTN) in floating gate flash memories beyond 20nm is studied comprehensively. Experiments reveal that the RTN would cause Vt distribution with a kinked tail which re-distributes to a "Gaussian-like" shape rapidly and was measured by the self established Budget Product Tester (BPT). A Multi-Times Verify (MTV) algorithm to mitigate the statistical tail, thus enlarging operation window is also exhibited by BPT. In further, a probability model to portray the compact Vt distribution under MTV is proposed. Finally, the impact of MTV on lowering the requirement of Error-correcting code (ECC) bit is also demonstrated.
Error Characterization and ECC Usage Relaxation beyond 20nm Floating Gate NAND Flash Memory
(2018-01-01)
Ku, S. H.
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Lin, T. W.
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Cheng, C. H.
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Lee, C. W.
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Chen, Ti-Wen
Endurance of floating gate flash memories at 19nm node and beyond is studied comprehensively. Experiments reveal that the random telegraph noise (RTN) would degrade the read margin with a tail, which quickly reshapes into a symmetric Gaussian form in a lightly-stressed state. After heavy stress, the lower part of tail would spread further while the upper part keeps roughly overlapped with that during fresh. This unique behavior, which was firstly measured by the self-established Budget Product Tester (BPT), can be explained by stress-induced hole trap creation. To investigate the impact of RTN on operation window, a novel algorithm of Multi-Times-Verify accompanied with the optimal Read-Retry (MTVR2) is proposed and validated by BPT. The advantage of MTVR2 to reduce the requirement of Error-Correcting Code (ECC) bit is demonstrated. Finally, the improvement of bit error rate (BER) in TLC operation with MTVR(2 )is also evaluated.
Investigation of charge loss in cycled NBit cells via field and temperature accelerations
(2006)
Tsai, W. J.
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Zous, N. K.
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Chen, H. Y.
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Liu, Lenvis
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Yeh, C. C.
In nitride storage flash memories, the high-V-T state retention loss induced by field and temperature acceleration is compared between single cells and products. Our result reveals that the charge loss path is the same no matter which accelerating methods is used. The traps created at the bottom oxide during P/E cycling provide such leak paths. In addition, the annealing of interface states would play a role in the V-T loss during high-temperature bake.
Overall Operation Considerations for a SONOS-based Memory
(2009)
Lee, C. H.
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Tu, W. H.
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Chong, L. H.
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Gu, S. H.
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Chen, K. F.
Erase characteristics of a SONOS-based structure are emulated not only for n(+)-poly and p(+)-poly gates but also for TaN-gate+Al2O3 combination. By incorporating our previous studies, performances including program, erase, and read disturb can be reviewed for both SONOS and TANOS devices. Unsurprisingly, it is hard to satisfy all requirements by using a SONOS device. In a TANOS device, an optimal bottom oxide thickness can be specified with the consideration of the three factors simultaneously. Moreover, it is found that conventional extrapolation methodology is inadequate to predict the lifetime of a TANOS device and tends to under-estimate the tolerable read bias.
Program Charge Effect on Random Telegraph Noise Amplitude and Its Device Structural Dependence in SONOS Flash Memory
(2009)
Chiu, J. P.
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Chou, Y. L.
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Ma, H. C.
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Wang, Tahui
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Ku, S. H.
Nitride program charge effects on random telegraph noise (RTN) in SONOS flash cells are investigated. We measure and simulate RTN amplitudes in floating gate flash, planar SONOS, and FinFET SONOS cells. We find that a planar SONOS has a wide spread in RTN amplitude after programming while a floating gate flash cell has identical RTN amplitude in erase and program states. The spread of program-state RTN amplitudes in a planar SONOS is attributed to a current-path percolation effect caused by random discrete nitride charges. The program-state RTN spread can be significantly reduced in FinFET SONOS.
Program Trapped-Charge Effect on Random Telegraph-Noise Amplitude in a Planar SONOS Flash Memory Cell
(2009-11-01)
Ma, H. C.
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Chou, Y. L.
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Chiu, J. P.
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Wang, Tahui
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Ku, S. H.
Program-charge effects in a SONOS Flash cell on the amplitude of random telegraph noise (RTN) are investigated. We measure RTN in 45 planar SONOS cells and 40 floating-gate (FG) cells in erase state and program state, respectively. We find that a SONOS cell has a wide spread in RTN amplitudes after programming, while an FG cell has identical RTN amplitudes in erase and program states at the same read-current level. A 3-D atomistic simulation is performed to calculate RTN amplitudes. Our result shows that the wide spread of program-state RTN amplitudes in a SONOS cell is attributed to a current-path-percolation effect caused by random discrete nitride charges.
Variations of V(t) Retention Loss in a SONOS Flash Memory Due to a Current-Path Percolation Effect
(2011-04-01)
Chou, Y. L.
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Chung, Y. T.
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Wang, Tahui
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Ku, S. H.
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Zou, N. K.
Discrete nitride program charge loss in a small-area SONOS Flash memory cell during retention is observed. Our measurement shows that a retention V(t) of a programmed SONOS cell exhibits a stepwise evolution with retention time. Individual single-program charge-loss-induced threshold voltage shifts (Delta V(t)) are characterized. We find the following: 1) The magnitude of Delta V(t) exhibits an exponential distribution, which is believed due to a current-path percolation effect caused by random program charges and substrate dopants, and 2) program-state V(t) retention loss has large variations in different cells and P/E cycles due to the percolation effect. We develop a Monte Carlo analysis to take into account the distribution of Delta V(t) and a tunneling front model to study the spread of a retention V(t) distribution in a SONOS Flash memory.
Variations of V-t Retention Loss in a SONOS Flash Memory Due to a Current-Path Percolation Effect
(2011-04-01)
Chou, Y. L.
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Chung, Y. T.
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Wang, Tahui
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Ku, S. H.
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Zou, N. K.
Discrete nitride program charge loss in a small-area SONOS Flash memory cell during retention is observed. Our measurement shows that a retention V-t of a programmed SONOS cell exhibits a stepwise evolution with retention time. Individual single-program charge-loss-induced threshold voltage shifts (Delta V-t) are characterized. We find the following: 1) The magnitude of Delta V-t exhibits an exponential distribution, which is believed due to a current-path percolation effect caused by random program charges and substrate dopants, and 2) program-state V-t retention loss has large variations in different cells and P/E cycles due to the percolation effect. We develop a Monte Carlo analysis to take into account the distribution of Delta V-t and a tunneling front model to study the spread of a retention V-t distribution in a SONOS Flash memory.