Browsing by Author "Lu, WT"

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Effects of low-temperature NH3 treatment on the characteristics of HfO2/SiO2 gate stack
(2005)
Lu, WT
;
Chien, CH
;
Huang, IJ
;
Yang, MJ
;
Lehnen, P
The effects of postdeposition low- temperature (400 degrees C) NH3 treatment (LTN treatment) on the characteristics of the HfO2/ SiO2 gate stack with the TiN gate electrode were studied in this work. After the HfO2 films were deposited using an AIXTRON Tricent atomic vapor deposition system, the LTN treatment was performed prior to the postdeposition annealing (PDA) step to prevent the growth of an additional interfacial layer, which is known to accompany the traditional high- temperature nitridation technique. The effective electrical oxide thickness for the devices annealed at 700 C PDA, either with or without LTN treatment, was estimated to be about 2.2 and 2.3 nm, respectively, without considering quantum effects. It was found that the LTN treatment effectively improves the characteristics of the HfO2/ SiO2 stack gates, such as capacitance- voltage (C-V) characteristics, frequency dispersion, trap generation rate, and dielectric breakdown voltage even at the high PDA temperature of 700 C. (c) 2005 The Electrochemical Society.
Improved reliability of HfO2/SiON gate stack by fluorine incorporation
(2006-04-01)
Lu, WT
;
Chiein, CH
;
Lan, WT
;
Lee, TC
;
Lehnen, P
Effects of fluorine (F) incorporation on the reliabilities of pMOSFETs with HfO2/SiON gate stacks have been studied. In this letter, fluorine was incorporated during the source/drain implant step and was diffused into the gate stacks during subsequent dopant activation. The authors found that F introduction only negligibly affects the fundamental electrical properties of the transistors, such as threshold voltage V-th, subthreshold swing, gate leakage current, and equivalent oxide thickness. In contrast, reduced generation rates in interface states and charge trapping under constant voltage stress and bias temperature stress were observed for the fluorine-incorporated split. Moreover, the authors demonstrated for the first time that F incorporation could strengthen the immunity against plasma charging damage.
Improvements on electrical characteristics of p-channel metal-oxide-semiconductor field effect transistors with HfO(2) gate stacks by post deposition N(2)O plasma treatment
(2005-11-01)
Lu, WT
;
Chien, CH
;
Lan, WT
;
Lee, TC
;
Yang, MJ
In this work, we found that employing a post deposition N(2)O plasma treatment following the deposition of HfO(2) film can effectively improve the electrical characteristics of p-type channel metal-oxide-semiconductor field-effect transistors (pMOSFETs) with a HfO(2) gate stack in terms of lower gate leakage current, lower interface state density, superior subthreshold swing, higher normalized transconductance and enhanced driving current even though it had led to a slightly higher equivalent oxide thickness (EOT) value of the HfO(2) gate stack by around 0.3 nm. In order to clarify the attributes of the improvements, we used charge pumping (CP) measurement to analyze the densities of interface states and bulk traps in the HfO(2) gate stacks. The improvements are then ascribed to the higher interface quality offered by the post deposition N(2)O plasma treatment. Moreover, we found that to more accurately estimate the bulk traps from the CP measurement, the leakage should be taken into account especially at low frequencies. Finally, it was found that the levels of the bulk traps and interface states can be reduced by the N(2)O plasma treatment, which also helps significantly eliminate the degradation of the gate stack during the subsequent voltage stress.
Improvements on electrical characteristics of p-channel metal-oxide-semiconductor field effect transistors with HfO2 gate stacks by post deposition N2O plasma treatment
(2005-11-01)
Lu, WT
;
Chien, CH
;
Lan, WT
;
Lee, TC
;
Yang, MJ
In this work, we found that employing a post deposition N2O plasma treatment following the deposition of HfO2 film can effectively improve the electrical characteristics of p-type channel metal-oxide-semiconductor field-effect transistors (pMOSFETs) with a HfO2 gate stack in terms of lower gate leakage current, lower interface state density, superior subthreshold swing, higher normalized transconductance and enhanced driving current even though it had led to a slightly higher equivalent oxide thickness (EOT) value of the HfO2 gate stack by around 0.3 nm. In order to clarify the attributes of the improvements, we used charge pumping (CP) measurement to analyze the densities of interface states and bulk traps in the HfO2 gate stacks. The improvements are then ascribed to the higher interface quality offered by the post deposition N2O plasma treatment. Moreover, we found that to more accurately estimate the bulk traps from the CP measurement, the leakage should be taken into account especially at low frequencies. Finally, it was found that the levels of the bulk traps and interface states can be reduced by the N2O plasma treatment, which also helps significantly eliminate the degradation of the gate stack during the subsequent voltage stress.
Process and doping species dependence of negative-bias-temperature instability for p-channel MOSFETs
(2002)
Lee, DY
;
Lin, HC
;
Chiang, WJ
;
Lu, WT
;
Huang, GW
The effects of poly-Si gate doping type and species on the negative-bias-temperature instability (NBTI) of p-channel MOS transistors were investigated. We found that, by properly suppressing boron penetration through careful thermal budget, NBTI can be reduced by proper fluorine incorporation. In addition, we found that NBTI is larger for devices with PMA annealing, thus clearly identified the role of hydrogen passivation in NBTI.
The characteristics of hole trapping in HfO2/SiO2 gate dielectrics with TiN gate electrode
(2004-10-18)
Lu, WT
;
Lin, PC
;
Huang, TY
;
Chien, CH
;
Yang, MJ
The characteristics of charge trapping during constant voltage stress in an n-type metal-oxide-semiconductor capacitor with HfO2/SiO2 gate stack and TiN gate electrode were studied. We found that the dominant charge trapping mechanism in the high-k gate stack is hole trapping rather than electron trapping. This behavior can be well described by the distributed capture cross-section model. In particular, the flatband voltage shift (DeltaV(fb)) is mainly caused by the trap filling instead of the trap creation [Zafar , J. Appl. Phys. 93, 9298 (2003)]. The dominant hole trapping can be ascribed to a higher probability for hole tunneling from the substrate, compared to electron tunneling from the gate, due to a shorter tunneling path over the barrier for holes due to the work function of the TiN gate electrode. (C) 2004 American Institute of Physics.