Browsing by Author "Lu, Wei-Siang"

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Investigating the degradation behavior caused by charge trapping effect under DC and AC gate-bias stress for InGaZnO thin film transistor
(2011-07-11)
Chen, Te-Chih
;
Chang, Ting-Chang
;
Hsieh, Tien-Yu
;
Lu, Wei-Siang
;
Jian, Fu-Yen
This letter investigates the degradation mechanism of amorphous indium-gallium-zinc oxide thin-film transistors under gate-bias stress. The larger V(t) shift under positive AC gate-bias stress when compared to DC operation indicates that an extra electron trapping mechanism occurs during rising/falling time during the AC pulse period. In contrast, the degradation behavior under illuminated negative gate-bias stress exhibits the opposite degradation tendency. Since electron and hole trapping are the dominant degradation mechanisms under positive and illuminated negative gate-bias stress, respectively, the different degradation tendencies under AC/DC operation can be attributed to the different trapping efficiency of electrons and holes. (C) 2011 American Institute of Physics. [doi: 10.1063/1.3609873]