Browsing by Author "Lu Chien-Yu"

Now showing 1 - 5 of 5

High load driving device
(2011-07-05)
Chuang Ching-Te
;
Lu Chien-Yu
A high load driving device is disclosed. The driving device comprises an inverter receiving a digital voltage. The inverter reverses the digital voltage, and then sends out it. The output terminal of the inverter is coupled to a capacitor, a first P-type field-effect transistor (FET), a second P-type FET, a first N-type FET, and a third N-type FET. A push-up circuit is composed of these transistors and a second N-type FET and coupled to a P-type push-up FET. A load is coupled to a high voltage through the P-type push-up FET. When the digital voltage rises from a low level to a high level, the push-up circuit utilizes the original voltage drop of the capacitor to control the P-type push-up FET, whereby the gate voltage of the P-type push-up FET is at a low stabilization voltage that is lower than the ground potential. Then, the load is driven rapidly.
STATIC MEMORY CELL
(2015-06-11)
Chuang Ching-Te
;
Chang Chih-Hao
;
Chung Chao-Kuei
;
Lu Chien-Yu
;
Jou Shyh-Jye
A static memory cell is provided. The static memory cell includes a data latch circuit and a voltage provider. The data latch circuit is configured to store a bit data. The data latch circuit has a first inverter and a second inverter, and the first inverter and the second inverter are coupled to each other. The first inverter and the second inverter respectively receive a first voltage and a second voltage as power voltages. The voltage provider provides the first voltage and the second voltage to the data latch circuit. When the bit data is written to the data latch circuit, the voltage provider adjusts a voltage value of one of the first and second voltages according to the bit data.
Static random access memory with data controlled power supply
(2012-11-27)
Chuang Ching-Te
;
Yang Hao-I
;
Hsia Mao-Chih
;
Lin Yung-Wei
;
Lu Chien-Yu
A static random access memory with data controlled power supply, which comprises a memory cell circuit and at least one Write-assist circuit, for providing power to the memory cell circuit according to data to be written to the memory cell circuit.
STATIC RANDOM ACCESS MEMORY WITH DATA CONTROLLED POWER SUPPLY
(2012-01-12)
Chuang Ching-Te
;
Yang Hao-I
;
Hsia Mao-Chih
;
Lin Yung-Wei
;
Lu Chien-Yu
A static random access memory with data controlled power supply, which comprises a memory cell circuit and at least one Write-assist circuit, for providing power to the memory cell circuit according to data to be written to the memory cell circuit.
Static random access memory with ripple bit lines/search lines for improving current leakage/variation tolerance and density/performance
(2014-07-08)
Chuang Ching-Te
;
Yang Hao-I
;
Lu Chien-Yu
;
Chen Chien-Hen
;
Chang Chi-Shin
A static random access memory includes a pre-charger, a first cell column array/peripheral circuit, and a first ripple buffer. The pre-charger is connected to a first local bit line in order to pre-charge the first local bit line. The first cell column array/peripheral circuit is connected to the first local bit line and has a plurality of cells for temporarily storing data. The cells are connected to the first local bit line. The first ripple buffer is connected to the first local bit line and a second local bit line in order to send the data from the first local bit line to the second local bit line.