Browsing by Author "Lue, Yi-Hsien"

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An oxide-buffered BE-MANOS charge-trapping device and the role of Al2O3
(2008)
Lai, Sheng-Chih
;
Lue, Hang-Ting
;
Liao, Chien-Wei
;
Huang, Yu-Fong
;
Yang, Ming-Jui
The role of Al2O3 in MANOS device is critically examined, and we conclude that its primary function is to reduce gate injection during erase operation. By itself, Al2O3 cannot stop charge leakage from the charge-trapping nitride layer. Furthermore, Al2O3 provides no magic during the erase operation, and MANOS erases very slowly through charge de-trapping. BE-SONOS [1], with the band engineered ONO tunneling layers, provides efficient channel hole injection for erase. BE-MANOS [2] should be an ideal combination with fast erase and good reliability. However, it shows poor data retention. By inserting a SiO2 buffer layer between Al2O3 and the SiN storage layer, the oxide-buffered BE-MANOS shows good performance and good reliability. The EOT scalability is also investigated.
Highly reliable MA BE-SONOS (Metal-Al2O3 bandgap engineered SONOS) using a SiO2 buffer layer
(2008)
Lai, Sheng-Chih
;
Lue, Hang-Ting
;
Liao, Chien-Wei
;
Wu, Tai-Bor
;
Yang, Ming-Jui
A Metal-high-K Bandgap-Engineered SONOS (MA BE-SONOS) with an additional SiO2 buffer layer is proposed. The thin SiO2 (5 similar to 6 nm) layer between the high-K (Al2O3) and nitride serves to prevent shallow trap generation. Contrary to the previously proposed MANOS or MA BE-SONOS devices using a simple high-k top dielectric, this composite structure eliminates the unstable high-K/nitride interface. Experimental results show that this new device can well suppress the erase saturation, just like MANOS. On the other hand, the data retention is greatly improved, owing to the much more stable interface between the nitride-trapping layer and top oxide. Very large memory window (> 7V) with excellent cycling endurance, read disturb immunity, and data retention has been successfully demonstrated. Theoretical model is also proposed to explain the principle of this device.
Reliability Study of MANOS with and without a SiO2 Buffer Layer and BE-MANOS Charge-Trapping NAND Flash Devices
(2009)
Liao, Chien-Wei
;
Lai, Sheng-Chih
;
Lue, Hang-Ting
;
Yang, Ming-Jui
;
Shen, Chin-Yen
The reliability of MANOS devices with an oxide buffer layer (MAONOS) in between SiN trapping layer and high-K Al2O3 top dielectric is extensively studied. We conclude that the primary function of high-K Al2O3 is to suppress the gate electron injection during erase instead of increasing the P/E speed. As a result, inserting a buffer oxide only changes EOT but does not change the P/E mechanisms. On the other hand, the buffer oxide can greatly improve data retention by suppressing leakage through Al2O3. However, owing to the slow erase performances with a thick bottom oxide, both MANOS and MAONOS erase slowly and very high erase voltages must be used. Also, both MANOS and MAONOS devices show very fast endurance degradation below P/E<10, which is inherent due to electron de-trapping mechanism. Moreover, the large erase voltage also causes severe degradation of tunnel oxide after many P/E cycling. To get both speed and reliability performances, it is necessary to introduce bandgap engineered tunneling barrier (BE-MANOS) to solve the fundamental problems of MANOS.
The Characteristics of n- and p-Channel Poly-Si Thin-Film Transistors with Fully Ni-Salicided S/D and Gate Structure
(2010)
Kuo, Po-Yi
;
Huang, Yan-Syue
;
Lue, Yi-Hsien
;
Chao, Tien-Sheng
;
Lei, Tan-Fu
n- and p-channel poly-Si thin-film transistors with fully Ni-self-aligned silicided (fully Ni-salicided) source/drain (S/D) and gate structure (n- and p-channel FUSA-TFTs) have been successfully fabricated on a 40 nm thick channel layer. The conventional poly-Si gate is replaced by the fully Ni-silicided gate, and the parasitic S/D resistance of the FUSA-TFTs is significantly reduced by the fully Ni-silicided S/D structure. The fully Ni-salicidation process is executed at a low temperature of 500 degrees C for a short rapid thermal annealing time. Experimental results show that the FUSA-TFTs give increased on/off current ratio, improved subthreshold characteristics, less threshold voltage roll-off, lower parasitic S/D resistance, higher gate capacitance, and larger field-effect mobility than conventional TFTs. The FUSA-TFTs effectively suppress the floating-body effect and parasitic bipolar junction transistor action. The characteristics of the FUSA-TFTs are suitable for three-dimensional integration applications and high performance driver circuits in the active-matrix liquid crystal displays. (C) 2009 The Electrochemical Society. [DOI: 10.1149/1.3258283] All rights reserved.