Browsing by Author "Luo, GL"

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A GeSi-buffer structure for growth of high-quality GaAs epitaxial layers on a Si substrate
(2005-01-01)
Chang, EY
;
Yang, TH
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Luo, GL
;
Chang, CY
;
材料科學與工程學系
A SiGe-buffer structure for growth of high-quality GaAs layers on a Si (100) substrate is proposed. For the growth of this SiGe-buffer structure. a 0.8-mum Si-0.1 Ge-0.9 layer was first grown. Because of the large mismatch between this layer and the Si substrate, many dislocations formed near the interface and in the low part of the Si0.1Ge0.9 layer. A 0.8-mum Si0.05Ge0.95 layer and a 1-mum top Ge layer were subsequently grown. The strained Si0.05Ge0.95/Si0.1Ge0.9 and Ge/Si0.05Ge0.95 interfaces formed can bend and terminate the upward-propagated dislocations very effectively. An in-situ annealing process is also performed for each individual layer. Finally, a 1-3-mum GaAs film was grown by metal-organic chemical vapor deposition (MOCVD) at 600degreesC. The experimental results show that the dislocation density in the top Ge and GaAs layers can be greatly reduced, and the surface was kept very smooth after growth, while the total thickness of the structure was only 5.1 mum (2.6-mum SiGe-buffer structure + 29.5-mum GaAs layer).
Controlled placement of self-organized Ge dots on patterned Si (001) surfaces
(2004-02-15)
Lee, HM
;
Yang, TH
;
Luo, GL
;
Chang, EY
;
材料科學與工程學系
The positioning and ordering of the self-organized Ge dots were controlled using the ultra high-vacuum chemical molecular epitaxial growth of Ge on electron beam lithographically patterned Si (001) substrates. The experimental results indicate that the edge smoothness of the etched Si holes affects the distribution and long-range ordering of the Ge dots formed. With optimized etching conditions, the Ge dots can be grown uniformly on the edges of the holes etched on the patterned Si substrates. The sizes of the Ge dots are approximately 10 nm. The proposed, technique can be applied to the fabrication of regimented arrays in signal processing applications.
Flower-like distributed self-organized Ge dots on patterned Si (001) substrates
(2003-06-15)
Lee, HM
;
Yang, TH
;
Luo, GL
;
Chang, EY
;
材料科學與工程學系
Self-organized Ge dots were obtained utilizing ultra high vacuum chemical molecular epitaxial growth of Ge on electron beam lithographically patterned Si (001) substrates. The dimensions of these etched Si mesa are 65/23/200 nm in diameter/height/period. The sizes and arrangement of the Ge dots were characterized by scanning electron microscopy and atomic force microscopy. The Ge dots have an average base width of 10 nm and the size is quite uniform. Due to the energetically favorable sites, the Ge dots tend to form homocentrically along the Si mesa edge, and their distribution is flower-like. [DOI: 10.1143/JJAP.42.L718].
Growth of high-quality GaAs epitaxial layers on Si substrite by using a novel GeSi buffer strucuture
(2004)
Chang, EY
;
Luo, GL
;
Yang, TH
;
材料科學與工程學系
;
Department of Materials Science and Engineering
A technique to grow high-quality GaAs layers on Si(100) substrate by using a novel SiGe buffer structure is proposed. For the growth of this SiGe buffer structure, a 0.8mum Si0.1Ge0.9,g layer was first grown. Due to the large mismatch between this layer and the Si substrate, many dislocations formed near the interface and in the low part of the Si0.1Ge0.(9) layer. A 0.8mum Si0.05Ge0.95 layer and a 1.0mum top Ge layer were subsequently grown. The Si0.05Ge0.95/Si0.1Ge0.9 and Ge/Si0.05Ge0.95 interfaces formed can bend and terminate the upward-propagated dislocations very effectively. The in situ annealing process is also performed for each individual layer after growth. Finally a 1-3mum GaAs film was grown by MOCVD at 650square. The experimental results show that the dislocation density in the top Ge and GaAs layers can be greatly reduced, and the surface was kept very smooth after growth, while the total thickness of the structure was kept relative thin after the growth (square3.0mum SiGe buffer struture+3.0mum GaAs layer).
Growth of high-quality Ge epitaxial layers on Si(100)
(2003-05-15)
Luo, GL
;
Yang, TH
;
Chang, EY
;
Chang, CY
;
Chao, KA
A method of growing high-quality epitaxial Ge layers on a Si(100) substrate is reported. In this method, a 0.8 mum Si0.1Ge0.9 layer was first grown. Due to the large lattice mismatch between this layer and the Si substrate, many dislocations form near the interface and in the lower part of the Si0.1Ge0.9 layer. A 0.8 mum Si0.05Ge0.95 layer and a 1.0 mum top Ge layer were subsequently grown on the Si0.1Ge0.9 layer. The formed interfaces of Si0.05Ge0.95/Si0.1Ge0.9 and Ge/Si0.05Ge0.95 can bend and terminate the upward-propagated dislocations very effectively. The in situ annealing process was also performed for each individual layer. Experimental results show that the dislocation density in the top Ge layer can be greatly reduced, and the surface is very smooth, while the total thickness of the structure is only 2.6 mum.
Growth of ZnSe epilayer on Si using Ge/GexSi1-x buffer structure
(2004-06-15)
Yang, TH
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Yang, CS
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Luo, GL
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Chou, WC
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Yang, TY
The epitaxial growth of ZnSe layers on Si substrates utilizing a Ge/Ge0.95Si0.0.5/Ge0.9Si0.1 buffer structure is demonstrated. In this study, we examine the structure, optical characteristics and atomic interdiffusion of the ZnSe epilayer grown on Si. In a sample with a 2degrees off-cut Si substrate, the outdiffusion of Ge into the ZnSe epilayer is suppressed. The low-temperature PL measurements indicate that the sample with a 2degrees off-cut Si substrate improves its optical characteristic effectively. The X-ray diffraction analysis and transmission electron microscopy (TEM) results indicate that the use of a 2degrees off-cut Ge/Ge0.95Si0.05/ Ge0.9Si0.1/Si substrate markedly improves the crystallinity of and reduced the number of threading dislocations in ZnSe grown on Si.
Interface-blocking mechanism for reduction of threading dislocations in SiGe and Ge epitaxial layers on Si(100) substrates
(2004-09-01)
Yang, TH
;
Luo, GL
;
Chang, EY
;
Hsieh, YC
;
Chang, CY
A mechanism of interface blocking was proposed to reduce the threading dislocations in the SiGe and Ge layers on Si(100) substrates. In this work, epitaxial Si1-xGex/Si1-(x-y)Gex-y and Ge/SiyGe1-y layers were grown by UHV/CVD. It was surprisingly found that if the variation of the Ge composition, y, across the interface of Si1-xGex/Si1-(x-y)Gex-y or Ge/SiyGe1-y is higher than a certain value, most of the threading dislocations appear to be blocked and confined in the underlying Si1-(x-y)Gex-y or SiGe1-y layer by the interface. It implies that this finding can provide a simple way to grow high-quality relaxed SiGe and Ge layers on the Si substrates. (C) 2004 American Vacuum Society.
Optical characterization of ZnSe epilayers and ZnCdSe/ZnSe quantum wells grown on Ge/Ge0.95Si0.05/Ge0.9Si0.1/Si virtual substrates
(2006-03-15)
Ku, JT
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Kuo, MC
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Shen, JL
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Chiu, KC
;
Yang, TH
Several approaches have been employed to grow high-quality ZnSe epilayers on Ge/Ge0.95Si0.05/Ge0.9Si0.1/Si virtual substrates. The ZnSe epilayers were characterized by photoluminescence spectroscopy. Migration enhanced epitaxy and inserting an in situ thermal annealing ZnSe buffer layer effectively reduced the intensity of deep level emissions from the ZnSe epilayer grown on a 6 degrees-tilted Ge/Ge0.95Si0.05/Ge0.9Si0.1/Si virtual substrate. Optimized conditions for growing high-quality ZnSe were used to deposit ZnCdSe/ZnSe multiple quantum wells on Ge/Ge0.95Si0.05/Ge0.9Si0.1/Si virtual substrates. Photoluminescence spectroscopy revealed quantum-confinement effect in the ZnCdSe multiple quantum wells. The evolution of the exciton emission peak energy and the linewidth as a function of temperature indicate a low density of localized sites in the sample with a well width of 1 nm. In the high-temperature regime, the thermal quenching of the excitonic emission intensity from ZnCdSe quantum well structures was governed by the thermal activation of carriers from quantum-well-confined states into barrier states. (c) 2006 American Institute of Physics.
Optimization of the growth of the InGaP etch-stop layer by MOVPE for InGaP/GaAs HBT device application
(2006-03-15)
Hsieh, YC
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Chang, EY
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Yeh, SS
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Chang, CW
;
Luo, GL
InGaP has high etching selectivity to GaAs. It can be used as the etch-stop layer to easily fabricate the InGaP/GaAs heterojunction bipolar transistors (HBTs). This process will also increase the uniformity and manufacturability of the HBT devices. However, the InGaP etch-stop layer will increase the energy barrier height that electrons have to overcome flowing from the collector to the subcollector, which will decrease the DC current gain of the device (T. Kobayashi, K. Taira, F. Nakamua, H. Kawai, J. Appl. Phys. 65 (1989) 4898). Therefore, the InGaP etch-stop layer has to be thin enough not to affect the device performance. But the spontaneous formation of the InxGa1-xAsyP1-y intermixing layer between GaAs/InGaP during the metal organic vapour-phase epitaxy (MOVPE) growth will affect the InGaP layer thickness needed as an effective etch-stop layer. In this paper, very thin InGaP layer was achieved with the suppression of InxGa1-xAsyP1-y formation by the optimization of the growth temperature and the gas switching sequence time. An effective 20 angstrom InGaP etch-stop layer was grown at 575 degrees C with interruption time of 3 s. Both STEM and PL data proved that the intermixing InxGa1-xAsyP1-y layer was eliminated and from the selective etching experiment, this 20 angstrom InGaP layer can stand 45 s etching by the H3PO4:H2O2:H2O = 1:1:20 solution. (c) 2005 Elsevier B.V. All rights reserved.
Study of nickel silicide contact on Si/Si1-xGex
(2003-09-01)
Yang, TH
;
Luo, GL
;
Chang, EY
;
Yang, TY
;
Tseng, HC
The properties of nickel silicide formed by depositing nickel on Si/P+ - Si1-xGex layer are compared with that of nickel germanosilicide on P+ - Si1-xGex layer formed by depositing Ni directly on P+ - Si1-xGex layer without silicon consuming layer. After thermal annealing, nickel silicide on Si/P+ S Si1-xGex layer shows lower sheet resistance and specific contact resistivity than that of nickel germanosilicide on P+ - Si1-xGex layer. In addition, small junction leakage current is also observed for nickel silicide on Si/P+ - Si1-xGex/N - Si diode. In summary, witha Si consuming layer on top of the Si1-xGex, the nickel silicide contact formed demonstrated improved electrical and materials characteristics as compared with the nickel germanosilicide contact which was formed directly on Si1-xGex layer.