Browsing by Author "Luo, Hsin-Yu"

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120V/ns Output Slew Rate Enhancement Technique and High Voltage Clamping Circuit in High Integrated Gate Driver for Power GaN FETs
(2015)
Yang, Hsiang-An
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Chiu, Chao-Chang
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Lai, Shin-Chi
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Chen, Jui-Lung
;
Chang, Chih-Wei
High power density is a key point that power converters endeavor to pursue. However, it is rare that gate driver of power converter can switch under high supply voltage with a fast operation frequency. In this paper, a half-bridge driver with the slew rate enhancement (SRE) technique is proposed and its switching frequency can be increased to 25MHz under a 700V supply voltage. Besides, the proposed high voltage clamping circuit ensures all circuits operating in a safe region without any overvoltage problems in the bootstrap operation. With specifically developed high voltage high speed (HVHS) process, high-side and low-side circuits can be well shielded by the isolation well which is embedded in the level shifter device to minimize chip size.
A Class-D Amplifier Powered by Embedded Single-Inductor Bipolar-Output Power Module with Low Common Noise and Dynamic Voltage Boosting Technique
(2014-01-01)
Chen, Shin-Hao
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Lin, Kuei-Liang
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Ng, Shao Siang
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Chen, Ke-Horng
;
Wey, Chin-Long
This paper proposes a high efficiency Class-D amplifier (CDA) with embedded single-inductor bipolar output (SIBO) power module. The characteristics of SIBO converter\'s bipolar outputs not only suppress equivalent common mode noise but also remove several large external bulky components in conventional boost supply CDA systems. Since bipolar outputs in the SIBO provide independent driving capability, CDA is capable of operating in both single-ended (SE) and bridge-tide load (BTL) configurations. Furthermore, the proposed dynamic voltage boosting (DVB) technique adjusts the SIBO output voltage level according to the CDA\'s output level with 5% power efficiency improvement. Peak total harmonic distortion plus noise (THD+N) performance is 0.012%. Peak power efficiency of SIBO and CDA are 89% and 93.2%, respectively.
A Dual-Level Dual-Phase Pulse-Width Modulation Class-D Amplifier with 0.001% THD, 112 dB SNR
(2014-01-01)
Yang, Shang-Hsien
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Yang, Yuan-Han
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Chen, Ke-Horng
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Hung, Chung-Chih
;
Wey, Chin-Long
this paper presents a dual-level dual-phase pulse-width modulation (DLDP PWM) Class-D audio amplifier circuit which enhance amplifier linearity and reduce distortion. The proposed DLDP PWM Class-D audio amplifier includes two sets of non-overlapping triangular waves, each at its respectful offset levels. Each set of triangular waves is composed of two 180 degrees out-of-phase triangular waves. The differential power stage consists of 8 power transistors, with voltage swings up to +/- 6V. Simulated results shows that the proposed DLDP PWM Class-D audio amplifier features an SNR up to 105 dB, and the THD is suppressed below 0.001 %, with the 3rd harmonic below -102 dBV.
A Low THD Clock-Free Class-D Audio Amplifier with an Increased Damping Resistor and Cross Offset Cancellation Technique
(2014-01-01)
Chou, Ying-Wei
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Chien, Meng-Wei
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Chen, Shin-Chieh
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Chen, Ke-Horng
;
Lin, Ying-Hsi
an increased damping resistor (IDR) replaces high-order loop filter to simply reduce the total harmonic distortion (THD) of Class-D audio amplifier. Besides, cross offset cancellation (COC) technique minimizes the system offset voltage to avoid dc current flows to the speaker in the bridge tied load (BTL) structure. Furthermore, variable switching frequency characteristic in self-oscillating modulation spreads the electro-magnetic interference (EMI) impact out on the output frequency spectrum. Experimental results demonstrate that the proposed Class-D amplifier can deliver 0.55W to the 8 Omega load with a 3.3V supply voltage with 150-nm CMOS process. The power efficiency is over 90% and the output THD is smaller than 0.01% (80dB).
A Power Cloud System (PCS) for High Efficiency and Enhanced Transient Response in SoC
(2013-03-01)
Shih, Chun-Jen
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Chu, Kuan-Yu
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Lee, Yu-Huei
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Chen, Wei-Chung
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Luo, Hsin-Yu
Tradeoff between power efficiency and transient performance usually comes out during the design consideration of a power module. A configurable power supplying implementation named as the power cloud system (PCS) is proposed to handle different load conditions for simultaneously improving the power efficiency and the transient response in order to meet the system-on-chip (SoC) requirements. At heavy loads, the switching regulator takes over the energy delivery scheme in the PCS with the fast transient technique. An auxiliary power unit, which activates hybrid operation in both medium and light loads, can realize the low-dropout (LDO) regulator to provide a supplementary energy immediately in transient duration and be the high-side power switches of the switching regulator to minimize the power loss. Besides, owing to its low quiescent current of an LDO regulator, it can directly operate under the ultralight-load condition. Therefore, the satisfactory power conversion efficiency and the load transient response can be derived over a wide load range, which will certainly meet the power requirement for different operated functions in the SoC. The chip was fabricated by a 0.25-mu m CMOS process, and the experimental results show the improvements of 56% transient dip voltage and 25% transient recovery time in hybrid operation, as well as a peak efficiency of 94%.
A Pseudo Fixed Switching Frequency 2kHz/A in Optimum On-Time Control Buck Converter with Predicting Correction Technique for EMI Solution
(2014-01-01)
Chen, Wei-Chung
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Lin, Kuei-Liang
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Chen, Ke-Horng
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Lin, Ying-Hsi
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Tsai, Tsung-Yen
This paper repots an optimum on-time (OOC) control with predicting correction technique (PCT) for ripple-based buck converter. The switching frequency (F-SW) variation is analyzed with completely considering the parasitic resistances of the components and devices. The proposed converter achieved nearly constant switching frequency over a wide load range without extra clock controlled circuits and current sensing circuits. The parameters of the parasitic resistances almost cause no influence and no restriction on F-SW performance. Actually, only the input voltage is necessary to predict the optimum on-time, and this work benefits the decease on total pin numbers. The simulation results demonstrate 0.375% Delta F-SW/F-SW and 2kHz/A Delta F-SW/Delta I-LOAD over 1.5A load current change. Consequently, pseudo constant F-SW with known noise spectrum strongly benefits the solution of electromagnetic interference (EMI) issue for system-on-chip (SoC).
Pseudo-Ramp Current Balance (PRCB) Technique With Offset Cancellation Control (OCC) in Dual-Phase DC-DC Buck Converter
(2014-10-01)
Su, Yi-Ping
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Chen, Wei-Chung
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Huang, Yu-Ping
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Lee, Yu-Huei
;
Chen, Ke-Horng
To cope with monolithic controller replicas and the current unbalance situation in multiphase converters, a pseudoramp current balance technique is proposed to achieve timemultiplexing current balance in voltage-mode multiphase DC-DC buck converter. With only one modulation controller, silicon area and power consumption caused by the replicas of controller can be reduced significantly. Current balance accuracy can be further enhanced since the mismatches between different controllers caused by process, voltage, and temperature variations are removed. Moreover, the offset cancellation control embedded in the current matching unit is used to eliminate intrinsic offset voltage existing at the operational transconductance amplifier for improved current balance. An explicit model, which contains both voltage and current balance loops with non-ideal effects, is derived for analyzing system stability. Experimental results show that current difference between each phase can be decreased by over 83% under both heavy and light load conditions.
Single Inductor Quad Output Switching Converter with Priority-Scheduled Program for Fast Transient and Unlimited-load Range in 40nm CMOS Technology
(2014-01-01)
Chen, Wei-Chung
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Huang, Tzu-Chi
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Tsai, Tsu-Wei
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Peng, Ruei-Hong
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Lin, Kuei-Liang
System-on-a-chip (SoC) applications need multiple power supplies with low noise for analog circuits and high efficiency for digital circuits. Thus, this paper proposes the priority-scheduled program (PSP) for single inductor quad output (SIQO) switching converter to manage energy delivery for four outputs. Consequently, SIQO converter with PSP can provides fast transient response and reduce cross-regulation. Besides, the level bypass detector (LBD) provides unlimited load range between each output through the shared inductor. The PSP cooperates with the LDB to transfer energy to low priority outputs to avoid overshoot at high priority outputs. With the two low-dropout regulator (LDR) working as buffers at low priority outputs, voltage disturbance can be filtered out. The SIQO converter fabricated in 40nm CMOS technology satisfies power requirements in portable electronics with 0.2% low noise, 15 mu s fast transient response, and cross-regulation smaller than 30mV.
Suppressing Output Overshoot Voltage Technique with 47.1mW/mu s Power-Recycling Rate and 93% Peak Efficiency DC-DC Converter for Multi-core Processors
(2015)
Chien, Meng-Wei
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Yang, Wen-Hau
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Chou, Ying-Wei
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Chen, Hsin-Chieh
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Chen, Wei-Chung
Conversion efficiency degrades in case of heavy-to-light loading change since state-of-art overshoot reduction techniques simply dissipate redundant energy at the output of buck DC-DC converter. Thus, the proposed dual-mode ripple-recovered compensator (D-RRC) and multi-phase suppressing output overshoot voltage (MP-SOOV) technique uses 33nH bondwire inductance to recycle energy and provides 47.1mW/mu s ultra-fast power-recycling rate to suppress overshoot voltage from 507mV to 95mV with 81.3% improvement when load changes from 1.7A to 0.3A. Experimental results show 93% high efficiency and high-speed operation with only tens of nano second on-time period.
Variable Sampling Slope (VSS) and No-Deadtime Ramp Generator (NDRG) Techniques for Closed-Loop Interleaving Power Factor Correction (PFC) Design with Suppression of Current Mismatch
(2012)
Chen, Chun-Yen
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Peng, Ruei Hong
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Tsai, Jen-Chieh
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Kang, Yu-Chi
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Ni, Chia-Lung
the proposed interleaving power factor correction (PFC) can effectively reduce the size of the AC-DC converter for portable electronics. Fully integrated variable sampling slope (VSS) technique can provide precise phase regulation under variable line voltage. Besides, the no-deadtime ramp generator (NDRG) records the previous status to modify the sequent on-time value to achieve current sharing for suppressing the total harmonic distortion (THD) and restraining the input current ripple, EMI filter, and the size of input inductor. Therefore, more power can be provided by the proposed interleaving PFC than that of single-phase PFC. Simultaneously, the drawback of the peak current twice than the average current in the Boundary control mode (BCM) can be greatly reduced. The test circuit fabricated in the TSMC 0.5 mu m 800V UHV process shows the highly integrated interleaving PFC can deliver high power of 180W with improved phase regulation precision.