Browsing by Author "Lv, Hangbing"

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Demonstration of 3D Vertical RRAM with Ultra Low-leakage, High-selectivity and Self-compliance Memory Cells
(2015)
Luo, Qing
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Xu, Xiaoxin
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Liu, Hongtao
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Lv, Hangbing
;
Gong, Tiancheng
Developing high performance self-selective cell (SSC) is one of the most critical issues of the integration of 3D vertical RRAM (V-RRAM). In this work, a four-layer V-RRAM array, with high performance HfO2/mixed ionic and electronic conductor (MIEC) bilayer SSC, was demonstrated for the first time. Several salient features were achieved, including ultra-low half-select leakage (<0.1 pA), very high nonlinearity (>10(3)), low operation current (nA level), self-compliance, high endurance (>10(7)), and robust read/write disturbance immunity.
Fully CMOS Compatible 3D Vertical RRAM with Self-aligned Self-selective Cell Enabling Sub-5nm Scaling
(2016)
Xu, Xiaoxin
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Luo, Qing
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Gong, Tiancheng
;
Lv, Hangbing
;
Long, Shibing
In low cost vertical resistive switching memory (VRRAM), the inter-layer leakage becomes a serious problem, primarily resulting from the ultimate scaling in the vertical dimension. In this work, for the first time, we present a novel approach of fabricating 3D VRRAM using self-aligned self-selective RRAM to effectively address such challenge. By successfully suppressing the inter-layer leakage, the scaling limit of VRRAM could be extended beyond 5 nm. Other benefits, such as high nonlinearity (> 10(3)), low power consumption (sub-mu A), robust endurance and excellent disturbance immunity, were also demonstrated.
Nonvolatile Crossbar 2D2R TCAM with Cell Size of 16.3 F-2 and K-means Clustering for Power Reduction
(2018-01-01)
Zhou, Keji
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Xue, Xiaoyong
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Yang, Jianguo
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Xu, Xiaoxin
;
Lv, Hangbing
A 28nm 16Kb nonvolatile ternary content addressable memory (nvTCAM) test chip based on logic-compatible resistive memory (ReRAM) is demonstrated with high density and low power for packet routing in network applications. The crossbar array exhibits a smallest cell size of 16.3F(2) by using 2-diode-2-ReRAM (2D2R) nvTCAM cell, useful for further 3-dimension (3D) stacking. K-means clustering is employed to allocate the storage of routing table entry for given bank count. Then the search of destination IP address can be classified and confined to a specific bank, reducing active banks for power saving. Evaluations show >3X improvement in cell density and >70% reduction in search energy with limited overhead in silicon area for bank count of four.
Recommended Methods to Study Resistive Switching Devices
(2019-01-01)
Lanza, Mario
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Wong, H-S Philip
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Pop, Eric
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Ielmini, Daniele
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Strukov, Dimitri
Resistive switching (RS) is an interesting property shown by some materials systems that, especially during the last decade, has gained a lot of interest for the fabrication of electronic devices, with electronic nonvolatile memories being those that have received the most attention. The presence and quality of the RS phenomenon in a materials system can be studied using different prototype cells, performing different experiments, displaying different figures of merit, and developing different computational analyses. Therefore, the real usefulness and impact of the findings presented in each study for the RS technology will be also different. This manuscript describes the most recommendable methodologies for the fabrication, characterization, and simulation of RS devices, as well as the proper methods to display the data obtained. The idea is to help the scientific community to evaluate the real usefulness and impact of an RS study for the development of RS technology.
Resistive random access memory (RRAM) technology: From material, device, selector, 3D integration to bottom-up fabrication
(2017-12-01)
Chen, Hong-Yu
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Brivio, Stefano
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Chang, Che-Chia
;
Frascaroli, Jacopo
;
Hou, Tuo-Hung
Emerging non-volatile memory technologies are promising due to their anticipated capacity benefits, non-volatility, and zero idle energy. One of the most promising candidates is resistive random access memory (RRAM) based on resistive switching (RS). This paper reviews the development of RS device technology including the fundamental physics, material engineering, three-dimension (3D) integration, and bottom-up fabrication. The device operation, physical mechanisms for resistive switching, reliability metrics, and memory cell selector candidates are summarized from the recent advancement in both industry and academia. Options for 3D memory array architectures are presented for the mass storage application. Finally, the potential application of bottom-up fabrication approaches for effective manufacturing is introduced.