Browsing by Author "Ma, DJ"

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A CMOS mismatch model and scaling effects
(1997-06-01)
Wong, SC
;
Pan, KH
;
Ma, DJ
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
In this letter, a novel single-pair mismatch model for short-channel MOS devices is developed, and scaling effects of mismatch distributions are investigated based on the model, Mismatch effect is modeled with threshold voltage, current factor, source resistance, and body factor mismatches, SPICE mismatch simulation is defined with mismatch parameters extracted from the model for accurate offset estimation in circuit simulation. Scaling effects with device size are investigated based on statistical mismatch data, and the results indicate that CMOS mismatch is induced by both local edge roughness and global variations, In addition, a root n-law model is developed for modeling gate-finger dependence of mismatch.
A CMOS mismatch model and scaling effects
(1997-06-01)
Wong, SC
;
Pan, KH
;
Ma, DJ
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
In this letter, a novel single-pair mismatch model for short-channel MOS devices is developed, and scaling effects of mismatch distributions are investigated based on the model, Mismatch effect is modeled with threshold voltage, current factor, source resistance, and body factor mismatches, SPICE mismatch simulation is defined with mismatch parameters extracted from the model for accurate offset estimation in circuit simulation. Scaling effects with device size are investigated based on statistical mismatch data, and the results indicate that CMOS mismatch is induced by both local edge roughness and global variations, In addition, a root n-law model is developed for modeling gate-finger dependence of mismatch.
An empirical three-dimensional crossover capacitance model for multilevel interconnect VLSI circuits
(2000-05-01)
Wong, SC
;
Lee, TGY
;
Ma, DJ
;
Chao, CJ
;
電子工程學系及電子研究所
We develop an empirical model for the crossover capacitance induced by the wire crossings in VLSI with multilevel metal interconnects. The crossover capacitance, which is formed in any three adjacent layers and of a three-dimensional (3-D) nature, is derived in closed form as a function of the wire geometry parameters. The total capacitance on a wire passing many crossings can then be easily determined by combining the crossover capacitance with the two-dimensional (2-D) intralayer coupling capacitance defined on a same layer. The model agrees well with the numerical field solver (with a 6.7% root-mean-square error) and measurement data (with a maximum error of 4.17%) for wire width and spacing down to 0.16 mu m and wire thickness down to 0.15 mu m. The model is useful for VLSI design and process optimization.
Modeling of interconnect capacitance, delay, and crosstalk in VLSI
(2000-02-01)
Wong, SC
;
Lee, GY
;
Ma, DJ
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Increasing complexity in VLSI circuits makes metal interconnection a significant factor affecting circuit performance. In this paper, we first develop new closed-form capacitance formulas for two major structures in very large scale integration (VLSI), namely, 1) parallel lines on a plane and 2) wires between two planes, by considering the electrical flux to adjacent wires and to ground separately. We then further derive closed-form solutions for the delay and crosstalk noise. The capacitance models agree well with numerical solutions of three-dimensional (3-D) Poisson's equation as well as measurement data. The delay and crosstalk models agree well with SPICE simulations.