Browsing by Author "Ma, Ming Wen"

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Carrier transportation mechanism of the TaN/HfO(2)/IL/Si structure with silicon surface fluorine implantation
(2008-07-01)
Wu, Woei Cherng
;
Lai, Chao-Sung
;
Wang, Tzu-Ming
;
Wang, Jer-Chyi
;
Hsu, Chih Wei
In this paper, the current transportation mechanism of HfO(2) gate dielectrics with a TaN metal gate and silicon surface fluorine implantation is investigated. Based on the experimental results of the temperature dependence of gate leakage current and Fowler-Nordheim tunneling characteristics at 77 K, we have extracted the current transport mechanisms and energy band diagrams for TaN/HfO(2)/IL/Si structures with fluorine incorporation, respectively. In particular, we have obtained the following physical quantities: 1) fluorinated and as-deposited interfacial layer (IL)/Si barrier heights (or conduction band offsets) at 3.2 and 2.7 eV; 2) TaN/fluorinated and as-deposited HfO(2) barrier heights at 2.6 and 1.9 eV; and 3) effective trapping levels at 1.25 eV (under both gate and substrate injections) below the HIM conduction band and at 1.04 eV (under gate injection) and 1.11 eV (under substrate injection) below the HfO(2) conduction band, which contributes to Frenkel-Poole conduction.
Current transport mechanism for HfO2 gate dielectrics with fluorine incorporation
(2008)
Wu, Woei Cherng
;
Lai, Chao Sung
;
Wang, Tzu Ming
;
Wang, Jer Chyi
;
Hsu, Chih Wei
In this article, the current transport mechanism of fluorinated HfO2 gate dielectrics is investigated. Based on the experimental results of the temperature dependence of gate leakage current and Fowler-Nordheim tunneling characteristics at 77 K, we have extracted the energy band diagrams and current transport mechanisms for TaN/HfOF/fluorinated-interfacial layer (IL)/Si structures. In particular, we have obtained the following quantities that will be useful for modeling and simulation: (i) fluorinated IL/Si barrier height (or conduction band offset): 3.2 eV; (ii) TaN/HfOF barrier height: 2.6 eV; and (iii) trap levels at 1.3 eV (under both gate and substrate injections) below the HfOF conduction band which contributes to Frenkel-Poole conduction. (C) 2007 The Electrochemical Society.
High-performance HfO2 gate dielectrics fluorinated by postdeposition CF4 plasma treatment
(2007)
Wu, Woei Cherng
;
Lai, Chao Sung
;
Wang, Jer Chyi
;
Chen, Jian Hao
;
Ma, Ming Wen
The superior characteristics of fluorinated HfO2 gate dielectrics were investigated. Fluorine was incorporated into HfO2 thin film by postdeposition CF4 plasma treatment to form fluorinated HfO2 gate dielectrics. Secondary-ion mass spectroscopy results showed that there was a significant incorporation of fluorine atoms at the TaN/HfO2 and HfO2/Si interface. Improvement of the gate leakage current, breakdown voltage, capacitance-voltage hysteresis, and charge trapping characteristics was observed in the fluorinated HfO2 gate dielectrics, with no increase of interfacial layer thickness. A physical model is presented to explain the improvement of hysteresis and the elimination of charge trapping. These results indicate that the fluorinated HfO2 gate dielectrics appear to be useful technology for future ultrathin gate dielectrics. (C) 2007 The Electrochemical Society.
Optimized ONO thickness for multi-level and 2-bit/cell operation for wrapped-select-gate (WSG) SONOS memory
(2008-01-01)
Wu, Woei-Cherng
;
Chao, Tien-Sheng
;
Peng, Wu-Chin
;
Yang, Wen-Luh
;
Chen, Jian-Hao
In this paper, highly reliable wrapped-select-gate (WSG) silicon-oxide-nitride-oxide-silicon (SONOS) memory cells with multi-level and 2-bit/cell operation have been successfully demonstrated. The source-side injection mechanism for WSG-SONOS memory with different ONO thickness was thoroughly investigated. The different programming efficiencies of the WSG-SONOS memory under different ONO thicknesses are explained by the lateral electrical field extracted from the simulation results. Furthermore, multi-level storage is easily obtained, and good V(TH) distribution presented, for the WSG-SONOS memory with optimized ONO thickness. High program/erase speed (10 mu s/5 ms) and low programming current (3.5 mu A) are used to achieve the multi-level operation with tolerable gate and drain disturbance, negligible second-bit effect, excellent data retention and good endurance performance.